Table of Contents

• A Low-Cost RF MIMO Test Method Using a Single Measurement Set-upErkan Acar, Sule Ozev, Kevin B. Redmond. 3-8 [doi]
• Non-RF to RF Test Correlation Using Learning Machines: A Case StudyHaralampos-G. D. Stratigopoulos, Petros Drineas, Mustapha Slamani, Yiorgos Makris. 9-14 [doi]
• RF Digital Signal Generation Beyond NyquistMarcelo Negreiros, Adão Antônio de Souza Jr., Luigi Carro, Altamiro Amadeu Susin. 15-22 [doi]
• Delay Test Quality Evaluation Using Bounded Gate DelaysSoumitra Bose, Vishwani D. Agrawal. 23-28 [doi]
• On Performance Testing with Path Delay PatternsBram Kruseman, Ananta K. Majhi, Guido Gronthoud. 29-34 [doi]
• Power Virus Generation Using Behavioral Models of CircuitsK. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula. 35-42 [doi]
• Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel WindowO. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 47-52 [doi]
• SDRAM Delay Fault Modeling and Performance TestingYu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu. 53-58 [doi]
• Optimizing Test Length for Soft Faults in DRAM DevicesZaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev. 59-66 [doi]
• Minimizing the Impact of Scan CompressionPeter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini. 67-74 [doi]
• Low Power Embedded Deterministic TestDariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer. 75-83 [doi]
• Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume ReductionAnshuman Chandra, Haihua Yan, Rohit Kapur. 84-92 [doi]
• On a New Outlier Rejection TechniqueClaude Thibeault. 97-103 [doi]
• Enhanced Resolution Jitter Testing Using Jitter ExpansionHyun Choi, Donghoon Han, Abhijit Chatterjee. 104-109 [doi]
• Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating CircuitHsiang-Hui Huang, Ching-Hwa Cheng. 110-118 [doi]
• A Programmable Window Comparator for Analog Online TestingAmit Laknaur, Rui Xiao, Haibo Wang. 119-124 [doi]
• Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator ErrorsMaryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee. 125-130 [doi]
• Error Tolerance in DNA Self-Assembly by (2k-1) x (2k-1) Snake Tile SetsXiaojun Ma, Jing Huang, Fabrizio Lombardi. 131-140 [doi]
• Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply VoltagesDaniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi. 145-150 [doi]
• Handling Pattern-Dependent Delay Faults in DiagnosisJyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou. 151-157 [doi]
• Diagnosis of Full Open Defects in Interconnecting LinesRosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi. 158-166 [doi]
• Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan TestV. R. Devanathan, C. P. Ravikumar, V. Kamakoti. 167-172 [doi]
• An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICsVikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland. 173-178 [doi]
• Supply Voltage Noise Aware ATPG for Transition Delay FaultsNisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram. 179-186 [doi]
• Test Set Reordering Using the Gate Exhaustive Test MetricKyoung Youn Cho, Edward J. McCluskey. 199-204 [doi]
• An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault TargetingJennifer Dworak. 205-210 [doi]
• Using Multiple Expansion Ratios and Dependency Analysis to Improve Test CompressionRichard Putman, Nur A. Touba. 211-218 [doi]
• Accelerating Diagnosis via Dominance Relations between Sets of FaultsRajsekhar Adapa, Spyros Tragoudas, Maria K. Michael. 219-224 [doi]
• Speeding Up Effect-Cause Defect Diagnosis Using a Small DictionaryWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang. 225-230 [doi]
• Using Scan-Dump Values to Improve Functional-Diagnosis MethodologyVishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang. 231-238 [doi]
• A UML Based System Level Failure Rate Assessment Technique for SoC DesignsMohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi. 243-248 [doi]
• An Analysis Framework for Transient-Error ToleranceJohn P. Hayes, Ilia Polian, Bernd Becker. 249-255 [doi]
• Case Study: Soft Error Rate Analysis in Storage SystemsBrian Mullins, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli, Kevin Granlund, Rudy Bauer, Scott Romano. 256-264 [doi]
• Silicon Evaluation of Static Alternative Fault ModelsChris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware. 265-270 [doi]
• Parameter Estimation for a Model with Both Imperfect Test and RepairSimon Wilson, Ben Flood, Suresh Goyal, Jim Mosher, Susan Bergin, Joseph O Brien, Robert Kennedy. 271-276 [doi]
• Circuit Failure Prediction and Its Application to Transistor AgingMridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra. 277-286 [doi]
• Transformer-Coupled Loopback Test for Differential Mixed-Signal SpecificationsByoungho Kim, Zhenhai Fu, Jacob A. Abraham. 291-296 [doi]
• Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware RadiosV. Natarajan, G. Srinivasan, A. Chatterjee, Craig Force. 297-302 [doi]
• Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus SignalLe Jin, Degang Chen, Randall L. Geiger. 303-310 [doi]
• High Level Synthesis of Degradable ASICs Using Virtual BindingNima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi. 311-317 [doi]
• Efficient RTL Coverage Metric for Functional Test SelectionJian Kang, Sharad C. Seth, Vijay Gangaram. 318-324 [doi]
• RTL Test Point Insertion to Reduce Delay Test VolumeKedarnath J. Balakrishnan, Lei Fang. 325-332 [doi]
• Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC CodeAvijit Dutta, Nur A. Touba. 349-354 [doi]
• A Built-In Self-Repair Scheme for Multiport RAMsTsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen. 355-360 [doi]
• Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMsA. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian. 361-368 [doi]
• Using Domain Partitioning in Wrapper Design for IP Cores Under Power ConstraintsThomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara. 369-374 [doi]
• Design of Test Access Mechanism for AMBA-Based System-on-a-ChipJaehoon Song, Piljae Min, Hyunbean Yi, Sungju Park. 375-380 [doi]
• TAM Design and Optimization for Transparency-Based SoC TestTomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara. 381-388 [doi]
• A Low Cost Spectral Power Extraction Technique for RF Transceiver TestingT.-L. Hung, J.-L. Huang. 389-394 [doi]
• Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response DetectionRajarajan Senguttuvan, Abhijit Chatterjee. 395-400 [doi]
• A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST ApplicationsYen-Chih Huang, Hsieh-Hung Hsieh, Liang-Hung Lu. 401-408 [doi]
• Automated Design and Insertion of Optimal One-Hot Bus EncodersPeter Wohl, John A. Waicukauski, Sanjay Patel. 409-415 [doi]
• Autoscan-Invert: An Improved Scan Design without External Scan Inputs or OutputsIrith Pomeranz, Sudhakar M. Reddy. 416-421 [doi]
• Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m})Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan. 422-430 [doi]
• DfT for the Reuse of Networks-on-Chip as Test Access MechanismAlexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes. 435-440 [doi]
• Novel Approach to Clock Fault Testing for High Performance MicroprocessorsCecilia Metra, Martin Omaña, T. M. Mak, Simon Tam. 441-446 [doi]
• At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-TesterMatthieu Tuna, Mounir Benabdenbi, Alain Greiner. 447-454 [doi]
• VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure ChipsSomnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia. 455-460 [doi]
• Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack ResistanceChunsheng Liu, Yu Huang. 461-468 [doi]