Abstract is missing.
- Triggering Trojans in SRAM circuits with X-propagationSenwen Kan, Jennifer Dworak. 1-8 [doi]
- Characterization of data retention faults in DRAM devicesAngelo Bacchini, Marco Rovatti, Gianluca Furano, Marco Ottavi. 9-14 [doi]
- Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessorsChuanlei Zheng, Shuai Wang. 15-20 [doi]
- Power droop reduction during Launch-On-Shift scan-based logic BISTMartin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche. 21-26 [doi]
- Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faultsMario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus. 27-32 [doi]
- Exploration of system availability during software-based self-testing in many-core systems under test latency constraintsMichael A. Skitsas, Chrysostomos Nicopoulos, Maria K. Michael. 33-39 [doi]
- Protecting cryptographic hardware against malicious attacks by nonlinear robust codesVictor Tomashevich, Yaara Neumeier, Raghavan Kumar, Osnat Keren, Ilia Polian. 40-45 [doi]
- CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assemblyMd. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, Mark Mohammad Tehranipoor. 46-51 [doi]
- Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-ChipJerry Backer, David Hély, Ramesh Karri. 52-56 [doi]
- Security methods in fault tolerant modified line graph based networksPrashant D. Joshi, Said Hamdioui. 57-62 [doi]
- A system-level scheme for resistance drift tolerance of a multilevel phase change memoryPilin Junsangsri, Jie Han, Fabrizio Lombardi. 63-68 [doi]
- Designs and analysis of non-volatile memory cells for single event upset (SEU) toleranceWei Wei, Fabrizio Lombardi, Kazuteru Namba. 69-74 [doi]
- Reliability estimation at block-level granularity of spin-transfer-torque MRAMsStefano Di Carlo, Marco Indaco, Paolo Prinetto, Elena I. Vatajelu, Rosa Rodríguez-Montañés, Joan Figueras. 75-80 [doi]
- Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variabilityHassen Aziza, Haithem Ayari, Santhosh Onkaraiah, Jean Michel Portal, Mathieu Moreau, Marc Bocquet. 81-85 [doi]
- Using memristor state change behavior to identify faults in photovoltaic arraysJimson Mathew, Marco Ottavi, Yunfan Yang, Dhiraj K. Pradhan. 86-91 [doi]
- TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-ChipAshkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, Nader Bagherzadeh. 92-97 [doi]
- Rescuing healthy cores against disabled routersMasoumeh Ebrahimi, Junshi Wang, Letian Huang, Masoud Daneshtalab, Axel Jantsch. 98-103 [doi]
- Fault tolerant and highly adaptive routing for 2D NoCsManoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Masoumeh Ebrahimi, Mark Zwolinski. 104-109 [doi]
- Performance sensor for tolerance and predictive detection of delay-faultsJorge Semião, David Saraiva, Carlos Leong, André Romão, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 110-115 [doi]
- Improved correction for hot pixels in digital imagersGlenn H. Chapman, Rohit Thomas, Rahul Thomas, Israel Koren, Zahava Koren. 116-121 [doi]
- Diagnosis of segment delay defects with current sensingWisam Aljubouri, Ahish Mysore Somashekar, Themistoklis Haniotakis, Spyros Tragoudas. 122-127 [doi]
- Scheduling algorithm in datapath synthesis for long duration transient fault toleranceTsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue. 128-133 [doi]
- Artificial intelligence based task mapping and pipelined scheduling for checkpointing on real time systems with imperfect fault detectionAnup Das 0001, Akash Kumar, Bharadwaj Veeravalli. 134-140 [doi]
- A probabilistic analysis of resilient reconfigurable designsAlirad Malek, Stavros Tzilis, Danish Anis Khan, Ioannis Sourdis, Georgios Smaragdos, Christos Strydis. 141-146 [doi]
- Domino effect protection on dataflow error detection and recoveryTiago A. O. Alves, Leandro A. J. Marzulo, Sandip Kundu, Felipe Maia Galvão França. 147-152 [doi]
- Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAsLucas A. Tambara, Fernanda Lima Kastensmidt, Paolo Rech, Christopher Frost. 153-158 [doi]
- A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAsStefano Di Carlo, Paolo Prinetto, Daniele Rolfo, Pascal Trotta. 159-164 [doi]
- Design and implementation of a self-healing processor on SRAM-based FPGAsMihalis Psarakis, Alexandros Vavousis, Cristiana Bolchini, Antonio Miele. 165-170 [doi]
- Aging analysis for recycled FPGA detectionHalit Dogan, Domenic Forte, Mark Mohammad Tehranipoor. 171-176 [doi]
- Analytic reliability evaluation for fault-tolerant circuit structures on FPGAsJahanzeb Anwer, Marco Platzner. 177-184 [doi]
- Estimating the effect of single-event upsets on microprocessorsCristian Constantinescu, Srini Krishnamoorthy, Tuyen Nguyen. 185-190 [doi]
- Unifying scan compressionSwapnil Bahl, Shreyans Rungta, Shray Khullar, Rohit Kapur, Anshuman Chandra, Salvatore Talluto, Pramod Notiyath, Ajay Rajagopalan. 191-196 [doi]
- Exploiting Intel TSX for fault-tolerant execution in safety-critical systemsFlorian Haas, Sebastian Weis, Stefan Metzlaff, Theo Ungerer. 197-202 [doi]
- Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systemsDomenico G. Sorrenti, Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Mario Porrmann, Cinzia Bernardeschi. 203-208 [doi]
- GPGPUs ECC efficiency and efficacyDaniel A. G. de Oliveira, Paolo Rech, Laércio Lima Pilla, Philippe Olivier Alexandre Navaux, Luigi Carro. 209-215 [doi]
- A runtime manager for gracefully degrading SoCsStavros Tzilis, Ioannis Sourdis. 216-221 [doi]
- A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNAYongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim. 222-227 [doi]
- A data recomputation approach for reliability improvement of scratchpad memory in embedded systemsHossein Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi. 228-233 [doi]
- Shortest path reduction in a class of uniform fault tolerant networksPrashant D. Joshi, Said Hamdioui. 234-239 [doi]
- SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCsMiao Tony He, Mohammad Tehranipoor. 240-245 [doi]
- Machine learning-based techniques for incremental functional diagnosis: A comparative analysisCristiana Bolchini, Luca Cassano. 246-251 [doi]
- A heuristic path selection method for small delay defects testPaniz Foroutatf, Mehdi Kamal, Zainalabedin Navabi. 252-257 [doi]
- Towards an adaptable bit-width NMR voter for multiple error maskingThiago Berticelli Lo, Fernanda Lima Kastensmidt, Antonio Carlos Schneider Beck. 258-263 [doi]
- Automated formal approach for debugging dividers using dynamic specificationMohammad Hashem Haghbayan, Bijan Alizadeh, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen. 264-269 [doi]
- Energy-efficient concurrent testing approach for many-core systems in the dark silicon ageMohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 270-275 [doi]
- A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatchIn-Seok Jung, Yong-Bin Kim. 276-280 [doi]
- Fault injection in the process descriptor of a Unix-based operating systemBartolomeo Montrucchio, Maurizio Rebaudengo, Alejandro Velasco. 281-286 [doi]
- An instance-based SER analysis in the presence of PVTA variationsBahareh J. Farahani, Saeed Safari. 287-292 [doi]
- Preemptive multi-bit IJTAG testing with reconfigurable infrastructureShahrzad Keshavarz, Amirreza Nekooei, Zainalabedin Navabi. 293-298 [doi]
- On the in-field functional testing of decode units in pipelined RISC processorsPaolo Bernardi, Riccardo Cantoro, Lyl M. Ciganda Brasca, Ernesto Sánchez, Matteo Sonza Reorda, Sergio de Luca, Renato Meregalli, Alessandro Sansonetti. 299-304 [doi]