Abstract is missing.
- Multi-Frequency Test Access Mechanism Design for Modular SOC TestingQiang Xu, Nicola Nicolici. 2-7 [doi]
- Rapid and Energy-Efficient Testing for Embedded CoresYinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra. 8-13 [doi]
- Constructing Transparency Paths for IP Cores Using Greedy Searching StrategyJianhui Xing, Hong Wang, Shiyuan Yang. 14-19 [doi]
- Adding Testability to an Asynchronous Interconnect for GALS SoCAristides Efthymiou, John Bainbridge, Douglas A. Edwards. 20-23 [doi]
- Test Power Reduction with Multiple Capture OrdersKuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho. 26-31 [doi]
- Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data PathsZhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara. 32-39 [doi]
- Low Power BIST with Smoother and Scan-Chain Reorder Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu. 40-45 [doi]
- Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power ReductionYoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu. 46-49 [doi]
- A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital ConvertersHsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang. 52-57 [doi]
- A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DACGuan-Xun Chen, Chung-Len Lee, Jwu E. Chen. 58-61 [doi]
- A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis PurposeHao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng. 62-67 [doi]
- A Built-In Loopback Test Methodology for RF Transceiver Circuits Using Embedded Sensor CircuitsSoumendu Bhattacharya, Abhijit Chatterjee. 68-73 [doi]
- Multiple Scan Tree Design with Test Vector ModificationKohei Miyase, Seiji Kajihara, Sudhakar M. Reddy. 76-81 [doi]
- An Efficient Low-Overhead Policy for Constructing Multiple Scan-ChainsJiann-Chyi Rau, Ching-Hsiu Lin, Jun-Yi Chang. 82-87 [doi]
- Scan-Based BIST Using an Improved Scan Forest ArchitectureDong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu. 88-93 [doi]
- The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test TimeIl-soo Lee, Yong Min Hur, Tony Ambler. 94-97 [doi]
- Testing for Missing-Gate Faults in Reversible CircuitsJohn P. Hayes, Ilia Polian, Bernd Becker. 100-105 [doi]
- Properties of Maximally Dominating FaultsIrith Pomeranz, Sudhakar M. Reddy. 106-111 [doi]
- I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement EnvironmentMasaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada. 112-117 [doi]
- High Level Fault Injection for Attack Simulation in Smart CardsKlaus Rothbart, Ulrich Neffe, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger. 118-121 [doi]
- Efficient Identification of Crosstalk Induced Slowdown TargetsMelvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian. 124-131 [doi]
- Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional NetsWichian Sirisaengtaksin, Sandeep K. Gupta. 132-139 [doi]
- A New Path Delay Test Scheme Based on Path Delay InertiaChung Liang Chen, Chung-Len Lee, Ming Shae Wu. 140-144 [doi]
- A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSIKatherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen. 145-150 [doi]
- Efficient Template Generation for Instruction-Based Self-Test of Processor CoresKazuko Kambe, Michiko Inoue, Hideo Fujiwara. 152-157 [doi]
- Test Instruction Set (TIS) for High Level Self-Testing of CPU CoresSaeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi. 158-163 [doi]
- A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGAChin-Lung Chuang, Dong-Jung Lu, Chien-Nan Jimmy Liu. 164-169 [doi]
- A Systematic Way of Functional Testing for VLSI ChipsShiyi Xu. 170-175 [doi]
- Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at FaultsChaowen Yu, Sudhakar M. Reddy, Irith Pomeranz. 178-183 [doi]
- A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD ToolSantosh Biswas, Siddhartha Mukhopadhyay, Amit Patra. 184-189 [doi]
- Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase ShiftersMasayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki. 190-195 [doi]
- Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant FaultsSukanta Das, Anirban Kundu, Biplab K. Sikdar. 196-201 [doi]
- Compactor Independent Direct DiagnosisWu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski. 204-209 [doi]
- Scan Chain Fault Identification Using Weight-Based Codes for SoC CircuitsS. Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang. 210-215 [doi]
- Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test SetHiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu. 216-221 [doi]
- Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on TestsYuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu. 222-227 [doi]
- Hybrid BIST Test Scheduling Based on Defect ProbabilitiesZhiyuan He, Gert Jervan, Zebo Peng, Petru Eles. 230-235 [doi]
- Pair Balance-Based Test Scheduling for SOCsYu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li. 236-241 [doi]
- RAIN (RAndom Insertion) Scheduling Algorithm for SoC TestJung-Been Im, Sunghoon Chun, Geunbae Kim, Jin-Ho Ahn, Sungho Kang. 242-247 [doi]
- March Based Memory Core Test Scheduling for SOCWei-Lun Wang. 248-253 [doi]
- An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time ConstraintStina Edbom, Erik Larsson. 254-257 [doi]
- On Test and Diagnostics of Flash MemoriesChih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu. 260-265 [doi]
- Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test SolutionLuigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan. 266-271 [doi]
- A Measurement Unit for Input Signal Analysis of SRAM Sense AmplifierYi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang. 272-276 [doi]
- An Efficient Diagnosis Scheme for Random Access MemoriesJin-Fu Li, Chao-Da Huang. 277-282 [doi]
- Evaluation of Intra-Word Faults in Word-Oriented RAMsSaid Hamdioui, John Delos Reyes, Zaid Al-Ars. 283-288 [doi]
- Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE ChannelJochen Rivoir. 290-295 [doi]
- A Low-Cost Diagnosis Methodology for Pipelined A/D ConvertersChih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang. 296-301 [doi]
- Reconfiguration for Enhanced ALternate Test (REALTest) of Analog CircuitsGanesh Srinivasan, Shalabh Goyal, Abhijit Chatterjee. 302-307 [doi]
- Dynamic Analog Testing via ATE Digital Test ChannelsC. C. Su, C. S. Chang, H. W. Huang, D. S. Tu, C. L. Lee, Jerry C. H. Lin. 308-312 [doi]
- Design and Implementation of Self-Testable Full Range Window ComparatorMike W. T. Wong, Yubin Zhang. 314-318 [doi]
- Efficient Test Methodologies for Conditional Sum AddersJin-Fu Li, Chih-Chiang Hsu. 319-324 [doi]
- A Novel Approach for On-line Testable Reversible Logic Circuit DesigD. P. Vasudevan, Parag K. Lala, James Patrick Parkerson. 325-330 [doi]
- Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple CoresSukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri. 331-334 [doi]
- Circuit-Width Based Heuristic for Boolean ReasoningGuanghui Li, Xiaowei Li. 336-341 [doi]
- Max-Testable Class of Sequential Circuits having Combinational Test Generation ComplexityDebesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara. 342-347 [doi]
- Classification of Sequential Circuits Based on ?k NotationChia Yee Ooi, Hideo Fujiwara. 348-353 [doi]
- A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic CircuitsShiy Xu, E. Edirisuriya. 354-357 [doi]
- Burn-In Stress Test of Analog CMOS ICsChin-Long Wey, Meng-Yao Liu. 360-365 [doi]
- Fail Pattern Identification for Memory Built-In Self-RepairRei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang. 366-371 [doi]
- Reduce Yield Loss in Delay Defect Detection in Slack IntervalHaihua Yan, Adit D. Singh. 372-377 [doi]
- Considering Fault Dependency and Debugging Time Lag in Reliability Growth Modeling during Software TestingChin-Yu Huang, Chu-Ti Lin, Chuan-Ching Sue. 378-383 [doi]
- Intelligible Test Techniques to Support Error-ToleranceMelvin A. Breuer. 386-393 [doi]
- Bounding Rollback-Recovery of Large Distributed Computation in WAN EnvironmentJin-Min Yang, Da-Fang Zhang. 394-399 [doi]
- Full Restoration of Multiple Faults in WDM Networks without Wavelength ConversionChuan-Ching Sue, Jun-Ying Yeh, Chin-Yu Huang. 400-405 [doi]
- On Improvement in Fault Tolerance of Hopfield Neural NetworksNaotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui. 406-411 [doi]
- Testing and Diagnosis Techniques for LUT-Based FPGA sShyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai. 414-419 [doi]
- Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case StudyDonghoon Han, Abhijit Chatterjee. 420-425 [doi]
- A Test Decompression Scheme for Variable-Length CodingHideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue. 426-431 [doi]
- Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan TestYouhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 432-437 [doi]
- Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip InterconnectsLei Wang, Sandeep K. Gupta, Melvin A. Breuer. 440-447 [doi]
- A Postprocessing Procedure of Test Enrichment for Path Delay FaultsIrith Pomeranz, Sudhakar M. Reddy. 448-453 [doi]
- Functional Scan Chain Design at RTL for Skewed-Load Delay Fault TestingHo Fai Ko, Nicola Nicolici. 454-459 [doi]
- Analysis and Attenuation Proposal in Ground BounceAntonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs. 460-463 [doi]