John Bainbridge - researchr alias

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Viewing Publication 1 - 11 from 11

2011

SpiNNaker: Design and Implementation of a GALS Multicore System-on-ChipLuis A. Plana, David M. Clark, Simon Davidson, Steve Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge. jetc, 7(4):17, 2011. [doi]

2008

An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net SimulatorLuis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu. nocs 2008: 215-216 [doi]

2007

Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral BusAndrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley. async 2007: 60-72 [doi]

2005

Test pattern generation and partial-scan methodology for an asynchronous SoC interconnectAristides Efthymiou, John Bainbridge, Douglas A. Edwards. tvlsi, 13(12):1384-1393, 2005. [doi]

Future Trends in SoC InterconnectSteve B. Furber, John Bainbridge. issoc 2005: [doi]

2004

Adding Testability to an Asynchronous Interconnect for GALS SoCAristides Efthymiou, John Bainbridge, Douglas A. Edwards. ats 2004: 20-23 [doi]

Sparse distributed memory using ::::N::::-of-::::M:::: codesStephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple. NN, 17(10):1437-1451, 2004. [doi]

2002

Chain: A Delay-Insensitive Chip Area InterconnectJohn Bainbridge, Stephen B. Furber. micro, 22(5):16-23, 2002. [doi]

1994

Defining Testability Metrics AxiomaticallyJohn Bainbridge. stvr, 4(2):63-80, 1994.

1992

A Heuristic Method for Generating Large Random ExpressionsJohn Bainbridge. ipl, 44(3):165-170, 1992.

1990

Obtaining Structural Metrics of Z Specifications for Systems DevelopmentJohn Bainbridge, R. W. Whitty, John Wordsworth. zum 1991: 269-281

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