Abstract is missing.
- Future Trends in SoC InterconnectSteve B. Furber, John Bainbridge. [doi]
- Design Methodologies and CAD Tool Flows for Networks on ChipsSrinivasan Murali. 1 [doi]
- Network-on-Chip: A New Paradigm for System-on-Chip DesignJari Nurmi. 2-6 [doi]
- System-level modeling and validation increase design productivity and save errorsBill Chown. 7 [doi]
- Low-Power SOC Design Using Configurable Processors-The Non-Nuclear OptionChris Rowen, Ashish Dixit, Steve Leibson. 8-13 [doi]
- Acceleration of Modular Exponentiation on System-on-a-Programmable-ChipPanu Hämäläinen, Ning Liu, Marko Hännikäinen, Timo D. Hämäläinen. 14-17 [doi]
- Instruction Folding for an Asynchronous Java Co-ProcessorTero Säntti, Juha Plosila. 18-21 [doi]
- Dynamic Verification of OCP-based SoCNatale Barsotti, Riccardo Mariani, Matteo Martinelli, Mario Pasquariello. 22 [doi]
- Reconfigurable Security Primitive for Embedded SystemsGuy Gogniat, Tilman Wolf, Wayne P. Burleson. 23-28 [doi]
- A FPGA Implementation of An Open-Source Floating-Point Computation SystemClaudio Brunelli, Fabio Garzia, Jari Nurmi, Claudio Mucci, Fabio Campi, Davide Rossi. 29-32 [doi]
- Multiplierless Reconfigurable Processing Element And Its Applications to DSP KernelsSangkyu Lee, Jeongeun Kim, Namsub Kim, Jinsang Kim, Won-Kyung Cho. 33-36 [doi]
- SOPC Builder, a Novel Design Methodology for IP IntegrationStefano Zammattio. 37 [doi]
- Proof of Concept for Low-power Digital Asynchronous IC DesignTommi J. Zetterman, Jukka T. Liimatainen, Jyrki T. Alamaunu. 38-41 [doi]
- Exploiting the Area X Performance Trade-off with Code CompressionEduardo Braulio Wanderley Netto, Eduardo Afonso Billo, Rodolfo Azevedo. 42-45 [doi]
- Application Specific Instruction Set Processor Microarchitecture for UTMS-FDD Cell SearchKimmo Puusaari. 46-49 [doi]
- Performance Modeling and Reporting for the UML 2.0 Design of Embedded SystemsPetri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen. 50-53 [doi]
- Providing Compilers and Application Program Support for Reconfigurable SoCs: Radical but OverdueAdeoye Olugbon, Tughrul Arslan, Iain Lindsay, Scott MacDougall. 54-57 [doi]
- Practical Assertion-based Formal Verification for SoC DesignsPing Yeung, Kenneth Larsen. 58-61 [doi]
- Static Estimation of Execution Times for Hardware Accelerators in System-on-ChipsMartin Holzer 0002, Markus Rupp. 62-65 [doi]
- Design-Time Application Exploration for MP-SoC Customized Run-Time ManagementChantal Ykman-Couvreur, Erik Brockmeyer, Vincent Nollet, Théodore Marescaux, Francky Catthoor, Henk Corporaal. 66-69 [doi]
- Overview of the 4S ProjectGerard J. M. Smit, Eberhard Schüler, Jürgen Becker 0001, Jérôme Quévremont, Werner Brugger. 70-73 [doi]
- Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable ArchitecturesArnaud Rivaton, Jérôme Quévremont, Qiwei Zhang, Pascal T. Wolkotte, Gerard J. M. Smit. 74-77 [doi]
- Run-time Mapping of Applications to a Heterogeneous SoCLodewijk T. Smit, Johann L. Hurink, Gerard J. M. Smit. 78-81 [doi]
- Energy Model of Networks-on-Chip and a BusPascal T. Wolkotte, Gerard J. M. Smit, Nikolay Kavaldjiev, Jens E. Becker, Jürgen Becker 0001. 82-85 [doi]
- SoC Leakage Power Reduction Algorithm by Input Vector ControlXiaotao Chang, Dongrui Fan, Yinhe Han, Zhimin Zhang. 86-89 [doi]
- ParLe - A Parallel Computing Learning Set for MPSOCs/NOCsMartti Forsell. 90-95 [doi]
- Towards a Formal Power Estimation Framework for Hardware SystemsJohanna Tuominen, Tero Säntti, Juha Plosila. 96-99 [doi]
- Predictive Synchronization Scheme between Simulator And Accelerator Free from Performance DeteriorationJae-Gon Lee, Ki-Yong Ahn, Chong-Min Kyung. 100-103 [doi]
- An Effective IP Reuse Methodology for Quality System-on-Chip DesignSoujanna Sarkar, Sanjay Shinde, Subash Chandar G.. 104-107 [doi]
- Interfacing UML 2.0 for Multiprocessor System-on-Chip Design FlowJouni Riihimäki, Petri Kukkala, Tero Kangas, Marko Hännikäinen, Timo D. Hämäläinen. 108-111 [doi]
- Architectural and Physical Design Optimizations for Efficient Intra-tile CommunicationAntonis Papanikolaou, F. Starzer, M. Miranda, Koenraad De Bosschere, Francky Catthoor. 112-115 [doi]
- Formal Modelling of Synchronous Hardware Components for System-on-ChipTomi Westerlund, Juha Plosila. 116-119 [doi]
- Rapid Refinable SoC SDR DesignPetri Isomäki, Nastooh Avessta. 120-123 [doi]
- Reliable Asynchronous Links for SoCEthiopia Nigussie, Juha Plosila, Jouni Isoaho. 124-127 [doi]
- Analysis of System Architecture of FPGA-based Embedded Controller for Magnetically Suspended RotorRafal Jastrzebski, Riku Pöllänen, Olli Pyrhönen. 128-132 [doi]
- FPGA Prototyping: Untapping Potential within the Multimillion-Gate System-on-Chip Design SpaceAntti Innamaa. 133-136 [doi]
- Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography SystemsMakoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura. 137-140 [doi]
- A Synchronization Coprocessor Architecture for WCDMA/OFDM Mobile Terminal ImplementationsLasse Harju, Jari Nurmi. 141-145 [doi]
- Hybrid Algorithm for Mapping Static Task Graphs on Multiprocessor SoCsHeikki Orsila, Tero Kangas, Timo D. Hämäläinen. 146-150 [doi]
- Efficiency of Leakage Reduction Techniques on Different Static Logic Styles for Embedded Portable Applications with High Standby to Active Time RatioSenthilkumar Jayapal, Shanthi Sudalaiyandi, Yiannos Manoli. 151-154 [doi]
- An On-Chip CDMA Communication NetworkXin Wang, Jari Nurmi. 155-160 [doi]
- High-Level Switching Activity Prediction Through Sampled Monitored SimulationFelipe Klein, Rodolfo Azevedo, Guido Araujo. 161-166 [doi]
- Exploitation of UML 2.0 - Based Platform Service Model and SystemC Workload Simulation in MPEG-4 PartitioningJari Kreku, Matti Eteläperä, Juha-Pekka Soininen. 167-170 [doi]
- An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-ChipTobias Bjerregaard, Shankar Mahadevan, Rasmus Grøndahl Olsen, Jens Sparsø. 171-174 [doi]
- A Formal Approach to Virtualisation and Provisioning in AMBA AHB-based Reconfigurable Systems-on-ChipAdeoye Olugbon, Tughrul Arslan, Iain Lindsay. 175-178 [doi]
- System-level Modeling of Wireless Integrated Sensor NetworksKashif Virk, Knud Hansen, Jan Madsen. 179-182 [doi]