Abstract is missing.
- High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data LinkRostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny. 3-14 [doi]
- Notes On Pulse SignalingJo C. Ebergen, Steve Furber, Arash Saifhashemi. 15-24 [doi]
- A Jitter Attenuating Timing ChainSuwen Yang, Mark R. Greenstreet, Jihong Ren. 25-38 [doi]
- The Vortex: A Superscalar Asynchronous ProcessorAndrew Lines. 39-48 [doi]
- Design of a High-Speed Asynchronous Turbo DecoderPankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel. 49-59 [doi]
- Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral BusAndrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley. 60-72 [doi]
- Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-ChipGwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet. 73-82 [doi]
- Gate-level modelling and verification of asynchronous circuits using CSPM and FDRMark B. Josephs. 83-94 [doi]
- The Design of a Genetic Muller C-ElementNam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener. 95-104 [doi]
- Delay/Phase Regeneration CircuitsCrescenzo D Alessandro, Andrey Mokhov, Alexandre V. Bystrov, Alexandre Yakovlev. 105-116 [doi]
- Area Optimizations for Dual-Rail Circuits Using Relative-Timing AnalysisTiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein. 117-128 [doi]
- A Cycle-Based Decomposition Method for Burst-Mode Asynchronous ControllersMelinda Y. Agyekum, Steven M. Nowick. 129-142 [doi]
- A Configurable Asynchronous Pseudorandom Bit Sequence GeneratorAlex Chow, William S. Coates, David Hopkins. 143-152 [doi]
- On-chip samplers for test and debug of asynchronous circuitsFrankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks. 153-162 [doi]
- A High Resolution Flash Time-to-Digital Converter Taking Into Account Process VariabilityNikolaos Minas, David Kinniment, Keith Heron, Gordon Russell. 163-174 [doi]
- Demystifying Data-Driven and Pausible Clocking SchemesRobert D. Mullins, Simon W. Moore. 175-185 [doi]
- Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global CommunicationAmitava Mitra, William F. McLaughlin, Steven M. Nowick. 186-195 [doi]
- Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous InterfacesWade L. Williams, Philip E. Madrid, Scott C. Johnson. 196-204 [doi]