Table of Contents

• Cryptanalysis of hardware based stream ciphers and implementation of GSM stream cipher to propose a novel approach for designing n-bit LFSR stream cipherDarshana Upadhyay, Trishla Shah, Priyanka Sharma. 1-6 [doi]
• Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cellRohan Sinha, Pranay Samanta. 1-6 [doi]
• Particle swarm optimization approach for low temperature BISTArpita Dutta, Santanu Chattopadhyay. 1-6 [doi]
• A fault tolerant test hardware for L1 cache module in tile CMPs architectureSaha Mousumi, Navneet Kumar Gautam, Biplab K. Sikdar. 1-6 [doi]
• Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technologyRakesh Trivedi, N. M. Devashrayee, Usha Sandeep Mehta, N. M. Desai, Himanshu Patel. 1-2 [doi]
• High power gain low noise amplifier design for next generation 1-7GHz wideband RF frontend RFIC using 0.18μm CMOSHasmukh P. Koringa, Bhushan D. Joshi, Vipul Shah. 1-5 [doi]
• High speed self biased current sense amplifier for low power CMOS SRAM'sMudasir Bashir, Sreehari Rao Patri, K. S. R. Krishna Prasad. 1-5 [doi]
• FPGA based disk controller and photon counter of optical polarimeterBinal B. Baraiya, Hiren K. Mewada, Amish B. Shah. 1-6 [doi]
• Sensitivity analysis of DRV for various configurations of SRAMRuchi, S. DasGupta. 1-5 [doi]
• A novel dual multiplier floating point multiply accumulate architectureRohit Kumar, Manisha Pattanaik. 1-2 [doi]
• Fabrication and characterization of pressure sensor, and enhancement of output characteristics by modification of operating pressure rangeS. Santosh Kumar, B. D. Pant. 1-4 [doi]
• Methodology for optimizing ESD protection for high speed LVDS based I/OsVishnuram Abhinav, Amitabh Chatterjee, Dheeraj Kumar Sinha, Rajan Singh. 1-5 [doi]
• Low power, high speed error tolerant multiplier using approximate addersKarri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha. 1-6 [doi]
• RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networksKrishnendu Guha, Debasri Saha, Amlan Chakrabarti. 1-6 [doi]
• A secure architecture for the design for testability structuresSamta D. Talatule, Pravin Zode, Pradnya Zode. 1-6 [doi]
• An efficient on-chip energy processing circuit for micro-scale energy harvesting systemsSaroj Mondal, Roy P. Paily. 1-5 [doi]
• A novel approach to reusable time-economized STIL based pattern developmentRahul Malhotra, Sujay Deb, Fabio Carlucci. 1-5 [doi]
• An embedded framework for accurate object localization using center of gravity measure with mean shift procedureJai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan. 1-6 [doi]
• An all digital delay lock loop architecture for high precision timing generatorMohammad Waris, Urvi Mehta, Rajiv Kumaran, Sanjeev Mehta, Arup Roy Chowdhury. 1-6 [doi]
• Partitioning-based test time reduction for core-based 3DICsSabyasachee Banerjee, Subhashis Majumder, Debesh K. Das. 1-5 [doi]
• Out of order floating point coprocessor for RISC V ISAVinayak Patil, Aneesh Raveendran, P. M. Sobha, A. David Selvakumar, D. Vivian. 1-7 [doi]
• Implementation of high speed radix-10 parallel multiplier using VerilogSonam Negi, Pitchaiah Madduri. 1-5 [doi]
• Standby leakage current estimation model for multi threshold CMOS inverter circuit in deep submicron technologyHari Sarkar, Sudakshina Kundu. 1-6 [doi]
• A low-power subthreshold LNA for mobile applicationsVinay M. M., Roy P. Paily, Anil Mahanta. 1-5 [doi]
• Measurement of de-assertion threshold of power-on-reset circuitsSanjay Kumar Wadhwa, Avinash Chandra Tripathi. 1-4 [doi]
• Molecular modeling of Nano bio p-i-n FETDebarati Dey, Pradipta Roy, Debashis De. 1-6 [doi]
• Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delayPradyumna Galgali, Surandra Rathod. 1-5 [doi]
• A methodology to reuse random IP stimuli in an SoC functional verification environmentV. S. Rashmi, Giridhar Somayaji, Sirisha Bhamidipathi. 1-5 [doi]
• RISC-V out-of-order data conversion co-processorAneesh Raveendran, Vinayak Patil, Vivian Desalphine, P. M. Sobha, A. David Selvakumar. 1-2 [doi]
• A novel adiabatic SRAM cell implementation using split level charge recovery logicS. Dinesh Kumar, S. K. Noor Mahammad. 1-2 [doi]
• Low power and hardware cost STUMPS BISTN. Ravi Kiran, G. Harish, A. Karthik, Siva Sankar Yellampalli. 1-4 [doi]
• Instruction cache design space exploration for embedded software applicationsRajendra Patel, Arvind Rajawat. 1-5 [doi]
• Area compact 5T portless SRAM cell for high density cache in 65nm CMOSJitendra Yadav, Pallavi Das, Abhinav Jain, Anuj Grover. 1-4 [doi]
• Modeling and synthesis of molecular memoryRenu Kumawat, Vineet Sahula, Manoj Singh Gaur. 1-2 [doi]
• An efficient approach for estimating the impact of SSO noise on LPDDR2 timing budgetYagya D. Mishra, Mohammad S. Hashmi, Akhilesh C. Mishra. 1-6 [doi]
• Design and implementation of DVB-S2 transport stream for onboard processing satelliteRangwani Varsha, Rajat Arora, T. V. S. Ram, Amit Patel. 1-6 [doi]
• A new row decoding architecture for fast wordline charging in NOR type Flash memoriesRohan Sinha, Bhawana Singh Nirwan, M. S. Hashmi. 1-5 [doi]
• Area optimized CMOS layouts of a 50 Gb/s low power 4: 1 multiplexerVibhor Pareek, Gaurvi Goyal. 1-6 [doi]
• Introduction to MEMS; their applications as sensors for chemical & bio sensingNitin S. Kale. 1-2 [doi]
• Implementation of a high speed multiplier for high-performance and low power applicationsG. Ganesh Kumar, Subhendu Kumar Sahoo. 1-4 [doi]
• Technology scaling and its side effectsAminul Islam. 1 [doi]
• GA based diagnostic test pattern generation for transition faultsAnupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur. 1-6 [doi]
• An inductorless receiver front-end for multiband wireless applicationsPriyanka Sharma, Sunil Pandey, Pravin A. Dwaramwar. 1-5 [doi]
• TSV aware standard cell placement for 3D ICsSameer Pawanekar, Gaurav Trivedi. 1-6 [doi]
• Intuitive design of PTAT and CTAT circuits for MOSFET based temperature sensor using Inversion Coefficient based approachShikhar Tewari, Kirmender Singh. 1-6 [doi]
• A novel VLSI design of DCTQ processor for FPGA implementationYogesh M. Jain, Aviraj R. Jadhav, Harish V. Dixit, Akshay S. Hindole, Jithin R. Vadakoott, Devendra Bilaye. 1-5 [doi]
• Timing model for two stage buffer and its application in ECSM characterizationYogesh Chaurasiya, Surabhi Bhargava, Arvind Sharma, Baljit Kaur, Bulusu Anand. 1-6 [doi]
• Novel design for wideband piezoelectric vibrational energy harvester (P-VEH)Shaurya Kaushal, Pulkit Kumar Dubey, Gaurav Prabhudesai, B. D. Pant. 1-5 [doi]
• On logic depth per pipelining stage with power aware flop, wave and hybrid pipelining with gate size and area constraintsPriyankar Talukdar. 1-6 [doi]
• Thermal aware AND-OR-XOR network synthesisPriyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan. 1-6 [doi]
• A 4 bit medium speed flash ADC using inverter based comparator in 0.18μm CMOSD. Malathi, R. Greeshma, R. Sanjay, B. Venkataramani. 1-5 [doi]
• Super-scale architecture enhancement of LEON3 core for DSP applicationJagrat Mehta, Anand D. Darji, T. V. S. Ram, Rajat Arora. 1-2 [doi]
• Modified low power scan based techniqueM. R. Gowthami, G. Harish, B. V. Bhargav Ram, Siva Sankar Yellampalli. 1-5 [doi]
• Real-time embedded systems analysis - From theory to practiceAnsuman Banerjee, Arijit Mondal, Arnab Sarkar, Santosh Biswas. 1-2 [doi]
• PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuitsToral Shah, Anzhela Matrosova, Virendra Singh. 1-2 [doi]
• A 2.47 GHz ultra NanoCrystaline diamond disk resonator with temperature compensation for RF applicationRajesh C. Junghare, Vinayak Pachkawade, Rajendra M. Patrikar. 1-2 [doi]
• Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technologyVijay Savani, N. M. Devashrayee. 1-2 [doi]
• SCL 180nm CMOS foundry: High reliability ASIC design for aerospace applicationsShri H. S. Jatana, Nilesh M. Desai. 1-2 [doi]
• Realistic dynamic timing verification for complex mixed signal hard macro's using UVMKunal Parihar, M. Venkatesh, Ravikumar Patel. 1-2 [doi]
• Performance study of side block oxide band gap engineered SONOS: A device simulation approachGagan Deep Verma, Manisha Pattanaik. 1-4 [doi]
• A pipelined memory-efficient architecture for face detection and tracking on a multicore environmentN. Sudha, D. Bharat Chandrahas. 1-2 [doi]
• An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidanceDebasis Dhal, Piyali Datta, Arpan Chakrabarty, Sudipta Roy, Rajat Kumar Pal. 1-6 [doi]
• A novel ROPUF for hardware securitySauvagya Ranjan Sahoo, Sudeendra Kumar, Kamalakanta Mahapatra. 1-2 [doi]
• Multi terminal net routing for island style FPGAs using nearly-2-SAT computationShyamapada Mukherjee, Suchismita Roy. 1-6 [doi]
• 2-DLM: Cache coherence aware dual link mesh for on-chip interconnectSonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Megha Bhargava. 1-2 [doi]
• Advanced UPF based voltage-aware verification for IOsRonak Patel, Amisha Naik, Amit Singh, Archana Arya, Pulkit Bhatnagar. 1-2 [doi]
• Bipolar voltage level shifterHari Shanker Gupta, Shweta Kirkire, Sunil Bhati, Ravi Shankar Chaurasia, Sanjeev Mehta, Arup Roy Choudhary, Dipen Patel, Jaymin Vaghela. 1-5 [doi]
• A novel two phase heuristic routing technique in digital microfluidic biochipSarit Chakraborty, Chandan Das, Susanta Chakraborty, Parthasarathi Dasgupta. 1-6 [doi]
• Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si3N4 ISFETR. Chaudhary, Amit Sharma, S. Sinha, Jitendra Yadav, R. Sharma, Ravindra Mukhiya, V. K. Khanna. 1-4 [doi]
• A cost-optimal algorithm for guard zone computation including detection and exclusion of overlappingRanjan Mehera, Arpan Chakraborty, Piyali Datta, Rajat Kumar Pal. 1-6 [doi]
• Designing efficient combinational compression architecture for testing industrial circuitsAnshuman Chandra, Santosh Kulkarni, Subramanian Chebiyam, Rohit Kapur. 1-6 [doi]
• Design and analysis of a touch mode MEMS capacitive pressure sensor for IUPCAnil Sharma. 1-6 [doi]
• Implementation of high speed radix-10 parallel multiplier using VerilogSonam Negi, Pitchaiah Madduri. 1-5 [doi]
• CORDIC on a configurable serial architecture for biomedical signal processing applicationsNupur Jain, Biswajit Mishra. 1-6 [doi]
• A Hamming code based technique to resolve the bit flip impact on compressed VLSI test data in IP core based SoCHarikrishna Parmar, Usha Mehta. 1-6 [doi]
• An offset-tolerant self-correcting sense amplifier for robust high speed SRAMPraneet Bhatia, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma. 1-6 [doi]
• Real time multisensor Laplacian fusion on FPGAKshitij Agrawal, Shubhajit Roy Chowdhury. 1-4 [doi]
• An integrable trench LDMOS transistor on SOI for RF power amplifiers in PICsMayank Punetha, Yashvir Singh. 1-4 [doi]
• MAC based FIR filter: A novel approach for low-power real-time de-noising of ECG signalsRamandeep Kaur, Rahul Malhotra, Sujay Deb. 1-5 [doi]
• A small bandwidth microelectromechanical ring resonator-based bandpass filterVinayak Pachkawade, Rajesh Junghare, Rajendra Patrikar. 1-5 [doi]
• Squarer design with reduced area and delayArindam Banerjee, Debesh Kumar Das. 1-6 [doi]
• Design and simulation of magnetic logic device for next generation data processingMadhav Rao, Neha Oraon, S. Ranganatha. 1-6 [doi]
• Detection and analysis of hardware trojan using scan chain methodMunishamanna Rithesh, G. Harish, B. V. Bhargav Ram, Siva Sankar Yellampalli. 1-6 [doi]
• Parallel two step random walk algorithm to analyze VLSI power grid networksSatyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar. 1-2 [doi]
• An improved AES Hardware Trojan benchmark to validate Trojan detection schemes in an ASIC design flowK. Sudeendra Kumar, Rakesh Chanamala, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra. 1-6 [doi]
• Design and simulative analysis of a batteryless Teflon coated capacitive pressure sensor for glaucoma diagnosisYericharla Mary Asha Latha, Gargi Khanna. 1-5 [doi]
• Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistorsPrashant Khot, Rajashekhar B. Shettar. 1-5 [doi]
• Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFTGovinda Rao Locharla, K. Sudeendra Kumar, K. K. Mahapatra, Samit Ari. 1-6 [doi]
• Improved supply regulation and temperature compensated current reference circuit with low process variationsSuraj Gupta, Sabir Ali Mondal, Hafizur Rahaman. 1-6 [doi]
• BONY: An algorithm to generate large synthetic combinational benchmark circuitsPriyankar Talukdar. 1-2 [doi]
• An efficient searching mechanism for dynamic NUCA in chip multiprocessorsKartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das. 1-5 [doi]
• Net weighing based timing driven standard cell placerSameer Pawanekar, Gaurav Trivedi. 1-6 [doi]
• Power- and thermal-aware testing of VLSI circuits and systemsSantanu Chattopadhyay. 1 [doi]
• A constructive heuristic for application mapping onto an express channel based Network-on-ChipSandeep D'Souza, Soumya J., Santanu Chattopadhyay. 1-6 [doi]
• Performance optimization of real time control systems using variable time periodJaishree Mayank, Arijit Mondal. 1-6 [doi]
• Defect characterization and testing of QCA devices and circuits: A surveyVaishali Dhare, Usha Mehta. 1-2 [doi]
• Fault masking in Quantum-dot cellular automata using prohibitive logic circuitRajdeep Kumar Nath, Bibhash Sen, Rachit Daga, Nilesh Chakraborty, Harsh Tibrewal, Biplab K. Sikdar. 1-5 [doi]
• On-chip CMOS temperature sensor with current calibrated accuracy of -1.1°C to +1.4°C (3σ) from -20°C to 150°CMudasir Bashir, Sreehari Rao Patri, K. S. R. Krishna Prasad. 1-5 [doi]
• Verilog-A implementation of energy-efficient SAR ADCs for biomedical applicationM. Santhanalakshmi, K. Yasoda. 1-6 [doi]
• Side channel attack resistant architecture for elliptic curve cryptographyPravin Zode, Raghavendra B. Deshmukh. 1-2 [doi]
• Network-on-chip: Current issues and challengesManoj Singh Gaur, Vijay Laxmi, Mark Zwolinski, Manoj Kumar, Niyati Gupta, Ashish Sharma. 1-3 [doi]
• A framework for thermal aware reliability estimation in 2D NoCAshish Sharma, Prachi Upadhyay, Ruby Ansar, Vijay Laxmi, Lava Bhargava, Manoj Singh Gaur, Mark Zwolinski. 1-6 [doi]
• High-performance multiplierless DCT architecture for HEVCAnand D. Darji, Raviraj P. Makwana. 1-5 [doi]
• Analysis and design guidelines for customized logic families in CMOSNamrata Singh, Sujay Deb. 1-2 [doi]
• Design of coherence verification unit for heterogeneous CMPsBidesh Chakraborty, Bhanu Pratap Singh, M. Chinnapureddy, Mamata Dalui, Biplab K. Sikdar. 1-6 [doi]
• Sensitivity and non-linearity study and performance enhancement in bossed diaphragm piezoresistive pressure sensorRamprasad Nambisan, S. Santosh Kumar, B. D. Pant. 1-6 [doi]
• Case study: Re-visiting SoC verification challenges and best practicesProkash Ghosh, Sandip Ghosh, Pritpal Singh, Saurabh Mishra. 1-9 [doi]
• Simulation and characterization of dual-gate SOI MOSFET, on-chip fabricated with ISFETJitendra Yadav, S. Sinha, Amit Sharma, R. Chaudhary, Ravindra Mukhiya, R. Sharma, V. K. Khanna. 1-5 [doi]
• Power aware cache miss reduction by energy efficient victim retentionShounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor. 1-6 [doi]
• Design and development of cantilever-type MEMS based piezoelectric energy harvesterShanky Saxena, Ritu Sharma, B. D. Pant. 1-4 [doi]
• Multicore processor - Architecture and programmingN. Sudha. 1-2 [doi]
• σLBDR: Congestion-aware logic based distributed routing for 2D NoCNiyati Gupta, Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Mark Zwolinski. 1-6 [doi]
• Low-leakage architecture for embedded ROMMansi S. Masrani, Raghavendra Chilukuri. 1-2 [doi]
• Transient current estimation using S3C (Standard cell current transient characterization)Michael Skaggs, Sushmita Kadiyala Rao, Ryan Robucci, Nilanjan Banerjee, Chintan Patel. 1-6 [doi]
• Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologiesArvind Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, Anand Bulusu. 1-6 [doi]