Priyanka Choudhury - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 8 from 8

2019

Thermal-Aware Partitioning and Encoding of Power-Gated FSMPriyanka Choudhury, Kanchan Manna, Vivek Rai, Sambhu Nath Pradhan. jcsc, 28(9):1950144, 2019. [doi]

2017

Transistor level realisation of power gated FSMSambhu Nath Pradhan, Priyanka Choudhury, Debanjali Nath. ijcaet, 9(3):351-371, 2017. [doi]

2016

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce PowerDebanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan. jcsc, 25(5), 2016. [doi]

2015

Thermal aware AND-OR-XOR network synthesisPriyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan. vdat 2015: 1-6 [doi]

2014

Power gating architecture implementation inside clock period to reduce powerDebanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan. ijcaet, 6(3):310-323, 2014. [doi]

2013

Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG)Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan. vdat 2013: 160-168 [doi]

2012

Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic AlgorithmPriyanka Choudhury, Sambhu Nath Pradhan. vdat 2012: 19-29 [doi]

An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding TogetherPriyanka Choudhury, Sambhu Nath Pradhan. jolpe, 8(4):452-463, 2012. [doi]

Sign in or sign up to see more results.

runs on WebDSL