Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan. Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). In Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi, Dharmendra Boolchandani, Virendra Singh, Adit D. Singh, editors, VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers. Volume 382 of Communications in Computer and Information Science, pages 160-168, Springer, 2013. [doi]
Abstract is missing.