Debanjali Nath - researchr alias

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Viewing Publication 1 - 8 from 8

2020

FPGA and ASIC realisation of EMD algorithm for real-time signal processingKaushik Das, Debanjali Nath, Sambhu Nath Pradhan. iet-cds, 14(6):741-749, 2020. [doi]

2017

Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power GatingAbhishek Nag, Debanjali Nath, Sambhu Nath Pradhan. jcsc, 26(3):1-12, 2017. [doi]

Transistor level realisation of power gated FSMSambhu Nath Pradhan, Priyanka Choudhury, Debanjali Nath. ijcaet, 9(3):351-371, 2017. [doi]

2016

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce PowerDebanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan. jcsc, 25(5), 2016. [doi]

2015

Thermal aware AND-OR-XOR network synthesisPriyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan. vdat 2015: 1-6 [doi]

Layout-oriented look up table-based dual threshold approach to reduce leakageSambhu Nath Pradhan, Angshuman Chakraborty, Abhishek Nag, Debanjali Nath. ijcaet, 7(4):456-480, 2015. [doi]

2014

Power gating architecture implementation inside clock period to reduce powerDebanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan. ijcaet, 6(3):310-323, 2014. [doi]

2013

Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG)Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan. vdat 2013: 160-168 [doi]

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