Table of Contents

• An Efficient High Frequency and Low Power Analog Multiplier in Current DomainAnu Gupta, Subhrojyoti Sarkar. 1-9 [doi]
• Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage RegulatorBiswajit Maity, Pradip Mandal. 10-18 [doi]
• Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic AlgorithmPriyanka Choudhury, Sambhu Nath Pradhan. 19-29 [doi]
• Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo DecodingRahul Shrestha, Roy Paily. 30-39 [doi]
• Low Complexity Encoder for Crosstalk Reduction in RLC Modeled InterconnectsGunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder. 40-45 [doi]
• Analog Performance Analysis of Dual-k Spacer Based Underlap FinFETAshutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta. 46-51 [doi]
• Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI ChipsR. Jayagowri, K. S. Gurumurthy. 52-58 [doi]
• Post-bond Stack Testing for 3D Stacked ICSurajit Kumar Roy, Dona Roy, Chandan Giri, Hafizur Rahaman. 59-68 [doi]
• Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence CheckerSoumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal. 69-78 [doi]
• Design of High Speed Vedic Multiplier for Decimal Number SystemPrabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya. 79-88 [doi]
• An Efficient Test Design for CMPs Cache Coherence Realizing MESI ProtocolMamata Dalui, Biplab K. Sikdar. 89-98 [doi]
• An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAsDebapriya Basu Roy, Debdeep Mukhopadhyay. 99-110 [doi]
• Arithmetic Algorithms for Ternary Number SystemSubrata Das, Parthasarathi Dasgupta, Samar Sen-Sarma. 111-120 [doi]
• SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ OutputDushyant Juneja, Sougata Kar, Procheta Chatterjee, Siddhartha Sen. 121-128 [doi]
• Design Optimization of a Wide Band MEMS Resonator for Efficient Energy HarvestingGoutam Rana, Samir Kumar Lahiri, Chirasree Roy Chaudhuri. 129-138 [doi]
• Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise MarginChandrabhan Kushwah, Santosh K. Vishvakarma. 139-146 [doi]
• Workload Driven Power Domain PartitioningArun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta, Chittaranjan A. Mandal. 147-155 [doi]
• Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor CircuitRituparna Dasgupta, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee, Chandan Kumar Sarkar. 156-165 [doi]
• A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLLManas Kumar Hati, Tarun Kanti Bhattacharyya. 166-171 [doi]
• ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational CircuitsJaynarayan T. Tudu, Deepak Malani, Virendra Singh. 172-179 [doi]
• Comparison of OpAmp Based and Comparator Based Switched Capacitor FilterManodipan Sahoo, Bharadwaj Amrutur. 180-189 [doi]
• Effect of Malicious Hardware Logic on Circuit ReliabilitySanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Pranav Singh. 190-197 [doi]
• A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing PowerP. R. Sruthi, M. Nirmala Devi. 198-208 [doi]
• Reusable and Scalable Verification Environment for Memory ControllersKiran Kumar Abburi, Siva Subrahmanya Evani, Sajeev Thomas, Anup Aprem. 209-216 [doi]
• Design of a Fault-Tolerant Conditional Sum AdderAtin Mukherjee, Anindya Sundar Dhar. 217-222 [doi]
• SEU Tolerant Robust Latch DesignMohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita. 223-232 [doi]
• Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect TransistorsDebaprasad Das, Avisek Sinha Roy, Hafizur Rahaman. 233-242 [doi]
• High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff CurvesAyantika Chatterjee, Indranil Sengupta. 243-251 [doi]
• A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS TechnologyMahendra Sakare, Mohit Singh, Shalabh Gupta. 252-257 [doi]
• VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual BasesHafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan. 258-269 [doi]
• A Synthesis Method for Quaternary Quantum Logic CircuitsSudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay. 270-280 [doi]
• On the Compact Designs of Low Power Reversible Decoders and Sequential CircuitsLafifa Jamal, Md. Masbaul Alam Polash, M. A. Mottalib, Hafiz Md. Hasan Babu. 281-288 [doi]
• Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube InterconnectsDebaprasad Das, Hafizur Rahaman. 289-299 [doi]
• A Fast FPGA Based Architecture for Sobel Edge DetectionSantanu Halder, Debotosh Bhattacharjee, Mita Nasipuri, Dipak Kumar Basu. 300-306 [doi]
• Speech Processor Design for Cochlear ImplantsArun Kumarappan, P. V. Ramakrishna. 307-316 [doi]
• An Efficient Technique for Longest Prefix Matching in Network RoutersRekha Govindaraj, Indranil Sengupta, Santanu Chattopadhyay. 317-326 [doi]
• A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase CutsBapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal. 327-336 [doi]
• Test Data Compression for NoC Based SoCs Using Binary Arithmetic OperationsSanga Chaki, Chandan Giri. 337-342 [doi]
• Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-ChipBibhas Ghoshal, Subhadip Kundu, Indranil Sengupta, Santanu Chattopadhyay. 343-349 [doi]
• An Efficient Multiplexer in Quantum-dot Cellular AutomataBibhash Sen, Manojit Dutta, Divyam Saran, Biplab K. Sikdar. 350-351 [doi]
• Integrated Placement and Optimization Flow for Structured and Regular LogicVikram Singh Saun, Suman Chatterjee, Anand Arunachalam 0001. 352-353 [doi]
• A Novel Symbol Estimation Algorithm for LTE StandardK. Kalyani, S. Rajaram. 354-356 [doi]
• Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit PerformanceNaushad Alam, Bulusu Anand, Sudeb Dasgupta. 357-359 [doi]
• A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology NodesBiswajit Patra, Sanatan Chattopadhyay, Amlan Chakrabarti. 360-363 [doi]
• Design and Implementation of Efficient Vedic Multiplier Using Reversible LogicP. Saravanan, P. Chandrasekar, Livya Chandran, Nikilla Sriram, P. Kalpana. 364-366 [doi]
• Design of Combinational and Sequential Circuits Using Novel Feedthrough LogicSauvagya Ranjan Sahoo, Kamala Kanta Mahapatra. 367-369 [doi]
• Efficient FPGA Implementation of Montgomery Multiplier Using DSP BlocksArpan Mondal, Santosh Ghosh, Abhijit Das, Dipanwita Roy Chowdhury. 370-372 [doi]
• Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFETNaveen Kaushik, Brajesh Kumar Kaushik, Davinder Kaur, Manoj Kumar Majumder. 373-374 [doi]
• VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale WatermarkSudip Ghosh 0001, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee, Hafizur Rahaman, Santi P. Maity. 375-376 [doi]
• A Photonic Network on Chip with CDMA LinksSoumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman. 377-378 [doi]
• Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect TransistorPartha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman, Parthasarathi Dasgupta. 379-380 [doi]
• Routing in NoC on Diametrical 2D Mesh ArchitecturePrasun Ghosal, Tuhin Subhra Das. 381-382 [doi]
• Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper)Rolf Drechsler, Robert Wille. 383-392 [doi]
• Power Problems in VLSI Circuit TestingFarhana Rashid, Vishwani D. Agrawal. 393-405 [doi]