K. S. Gurumurthy - researchr alias

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Viewing Publication 1 - 10 from 10

2013

Instruction Level Power Analysis for Low Power VLSI ApplicationsPrashant V. Joshi, N. Prameela Kumari, K. S. Gurumurthy. icetet 2013: 52-53 [doi]

Realization of Basic Gates Using Universal Logic Blocks in Quantum Dot Cellular AutomataN. Prameela Kumari, Prashant V. Joshi, K. S. Gurumurthy. icetet 2013: 50-51 [doi]

2012

Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI ChipsR. Jayagowri, K. S. Gurumurthy. vdat 2012: 52-58 [doi]

2011

Design of High Performance Quaternary AddersK. S. Vasundara Patel, K. S. Gurumurthy. ismvl 2011: 22-26 [doi]

2010

Sub Band Speech Analysis Using Gammatone Filter Banks and Optimal Pitch Extraction Methods for Each Sub Band Using Average Magnitude Difference Function (AMDF) for LPC Speech Coders in Noisy EnvironmentsSuma S. A., K. S. Gurumurthy. jnit, 1(2):13-24, 2010. [doi]

New Improved Echo Canceller Based on Normalized LMS Adaptive Filter for Single Talk and Double Talk Detection, Subband Echo Cancellation, Acoustic Echo CancellationSuma S. A., K. S. Gurumurthy. jnit, 1(2):61-74, 2010. [doi]

2009

Load Balancing towards ECU IntegrationRajeshwari Hegde, K. S. Gurumurthy. artcom 2009: 521-524 [doi]

Load Balancing in Multi ECU ConfigurationRajeshwari Hegde, K. S. Gurumurthy. artcom 2009: 103-106 [doi]

Moving From Binary Towards Multi-valued logicK. S. Vasundara Patel, K. S. Gurumurthy. cdes 2009: 24-30

2003

Artificial neural networks as building blocks of mixed signal FPGAR. Manjunath, K. S. Gurumurthy. fpt 2003: 375-378 [doi]

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