Area compact 5T portless SRAM cell for high density cache in 65nm CMOS - researchr publication

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Jitendra Yadav, Pallavi Das, Abhinav Jain, Anuj Grover. Area compact 5T portless SRAM cell for high density cache in 65nm CMOS. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-4, IEEE, 2015. [doi]

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