Vinayak Patil, Aneesh Raveendran, P. M. Sobha, A. David Selvakumar, D. Vivian. Out of order floating point coprocessor for RISC V ISA. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-7, IEEE, 2015. [doi]
Abstract is missing.