Vinayak Patil, Aneesh Raveendran, P. M. Sobha, A. David Selvakumar, D. Vivian. Out of order floating point coprocessor for RISC V ISA. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-7, IEEE, 2015. [doi]
@inproceedings{PatilRSSV15,
title = {Out of order floating point coprocessor for RISC V ISA},
author = {Vinayak Patil and Aneesh Raveendran and P. M. Sobha and A. David Selvakumar and D. Vivian},
year = {2015},
doi = {10.1109/ISVDAT.2015.7208116},
url = {http://dx.doi.org/10.1109/ISVDAT.2015.7208116},
researchr = {https://researchr.org/publication/PatilRSSV15},
cites = {0},
citedby = {0},
pages = {1-7},
booktitle = {19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015},
publisher = {IEEE},
isbn = {978-1-4799-1743-3},
}