Table of Contents

• A SystemC-AMS Development Framework for High Power IC Test-HardwareDavide Turossi, Andrea Baschirotto. 1-5 [doi]
• Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area ImpactSandeep Kumar Goel, Ankita Patidar, Frank Lee. 1-4 [doi]
• Relation Coverage: A New Paradigm for Hardware/Software TestingChristoph Hazott, Daniel Große. 1-4 [doi]
• Extracting Weights of CIM-Based Neural Networks Through Power Analysis of Adder-TreesFouwad Jamil Mir, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil. 1-4 [doi]
• A Novel Power Analysis Attack against CRYSTALS-Dilithium ImplementationYong Liu, Yuejun Liu, Yongbin Zhou, Yiwen Gao 0001, Zehua Qiao, Huaxin Wang. 1-6 [doi]
• Silent Data Corruptions in Computing Systems: Early Predictions and Large-Scale MeasurementsDimitris Gizopoulos, George Papadimitriou 0001, Odysseas Chatzopoulos, Nikos Karystinos, Harish Dattatraya Dixit, Sriram Sankar. 1-10 [doi]
• Formal Resilience Metric Characterization in Complex Digital SystemsDamiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory. 1-4 [doi]
• Test and Repair Improvements for UCIeTsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen. 1-6 [doi]
• Lifecycle Management of Emerging MemoriesMoritz Fieback, Letícia Maria Veiras Bolzani Poehls. 1-6 [doi]
• Analyzing the Structural and Operational Impact of Faults in Floating-Point and Posit Arithmetic Cores for CNN OperationsJosie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Robert Limas Sierra, Matteo Sonza Reorda. 1-4 [doi]
• Combining Built-In Redundancy Analysis with ECC for Memory TestingLuc Romain, Paul-Patrick Nordmann, Benoit Nadeau-Dostie, Lori Schramm, Martin Keim. 1-6 [doi]
• Test Compression for Neuromorphic ChipsXin-Ping Chen, Hsu-Yu Huang, Chu-Yun Hsiao, Jennifer Shueh-Inn Hu, James Chien-Mo Li. 1-6 [doi]
• What Would Interactive Testing With 1687 Look Like?Michele Portolan, Martin Keim, J. F. Coté, Hans-Martin Von Staud. 1 [doi]
• A Concept of Provably Detected Defects for Analog Defect Simulation Campaign ImprovementVladimir A. Zivkovic, Inga Abel, Anthony Candage. 1-4 [doi]
• Modeling Thermal Effects For Biasing PUFsAghiles Douadi, Elena Ioana Vatajelu, Paolo Maistri, David Hély, Vincent Beroulle, Giorgio Di Natale. 1-4 [doi]
• Characterization of Ultra-low Random Jitter Reduction Methods up to 36 GHzDavid C. Keezer, Dany Minier, Hongjie Li. 1-6 [doi]
• It is All About Trust: The Road to Autonomous Driving Will Connect Test, Reliability and SafetyJuergen Alt. 1 [doi]
• Design-for-Test for Intermittent Faults in STT-MRAMsSicong Yuan, Mohammad Amin Yaldagard, Hanzhi Xun, Moritz Fieback, Erik Jan Marinissen, Woojin Kim, Siddharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui. 1-6 [doi]
• Time and Space Optimized Storage-based BIST under Multiple Voltages and VariationsHanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich. 1-6 [doi]
• Silent Data Corruption from Timing Marginalities Due to Process VariationsAdit D. Singh. 1-7 [doi]
• Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration SpaceAlessandro Veronesi, Alessandro Nazzari, Dario Passarello, Milos Krstic, Michele Favalli, Luca Cassano, Antonio Miele, Davide Bertozzi, Cristiana Bolchini. 1-6 [doi]
• Faulty Function Extraction for Defective CircuitsChris Nigh, Ruben Purdy, Wei Li, Subhasish Mitra, R. D. Shawn Blanton. 1-6 [doi]
• AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN AcceleratorsMahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin. 1-4 [doi]
• A Multi-Objective Evolutionary Approach for Test Network DesignPayam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn 0001, Rolf Drechsler. 1-4 [doi]
• Post-Manufacture Criticality-Aware Gain Tuning of Timing Encoded Spiking Neural Networks for Yield RecoveryAnurup Saha, Kwondo Ma, Chandramouli N. Amarnath, Abhijit Chatterjee. 1-4 [doi]
• Hardening Bus-Encoders with Power-Aware Single Error Correcting CodesShlomo Engelberg, Osnat Keren. 1-4 [doi]
• On-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory ComputingGaurav Singh, Omar Numan, Dipesh C. Monga, Martin Andraud, Kari Halonen. 1-6 [doi]
• Fault Sensitivity Analysis of Printed Bespoke Multilayer Perceptron ClassifiersPriyanjana Pal, Florentia Afentaki, Haibin Zhao, Gurol Saglam, Michael Hefenbrock, Georgios Zervakis 0001, Michael Beigl, Mehdi B. Tahoori. 1-6 [doi]
• Silent Data Corruption Errors in VLSI Circuits: Implications, Challenges, and OpportunitiesRama Govindaraju. 1 [doi]
• Approximate Fault-Tolerant Neural Network SystemsMarcello Traiola, Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Bastien Deveautour, Ernesto Sánchez 0001, Alberto Bosio, Sepide Saeedi, Alessio Carpegna, Anil Bayram Gogebakan, Enrico Magliano, Alessandro Savino. 1-10 [doi]
• Reliability and Security of AI HardwareDennis Gnad, Martin Gotthard, Jonas Krautter, Angeliki Kritikakou, Vincent Meyers, Paolo Rech, Josie E. Rodriguez Condia, Annachiara Ruospo, Ernesto Sánchez 0001, Fernando Fernandes dos Santos, Olivier Sentieys, Mehdi B. Tahoori, Russell Tessier, Marcello Traiola. 1-10 [doi]
• Optimizing System-Level Test Program Generation via Genetic ProgrammingDenis Schwachhofer, Francesco Angione, Steffen Becker 0001, Stefan Wagner 0001, Matthias Sauer 0002, Paolo Bernardi, Ilia Polian. 1-4 [doi]
• AMS Test Stimulus Generation and Response Analysis Using Hyperdimensional Clustering: Minimizing Misclassification RateSuhasini Komarraju, Mohamed Mejri, Akhil Tammana, Gowsika Dharmaraj, Chandramouli N. Amarnath, Abhijit Chatterjee. 1-4 [doi]
• MBIST-based weak bit screening method for embedded MRAMJongsin Yun, Sina Bakhtavari Mamaghani, Mehdi B. Tahoori, Christopher Münch, Martin Keim. 1-4 [doi]
• Polynomial Formal Verification of Approximate Adders with Constant CutwidthMohamed Nadeem, Chandan Kumar Jha 0001, Rolf Drechsler. 1-6 [doi]
• Error Detection and Correction Codes for Safe In-Memory ComputationsLuca Parrini, Taha Soliman, Benjamin Hettwer, Jan Micha Borrmann, Simranjeet Singh, Ankit Bende, Vikas Rana, Farhad Merchant, Norbert Wehn. 1-4 [doi]
• Silent Data Corruption: Test or Reliability Problem?Erik Jan Marinissen, Harish Dattatraya Dixit, Ronald Shawn Blanton, Aaron Kuo, Wei Li, Subhasish Mitra, Chris Nigh, Ruben Purdy, Ben Kaczer, Dishant Sangani, Pieter Weckx, Philippe J. Roussel, Georges G. E. Gielen. 1-7 [doi]
• Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural NetworksSoyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori. 1-6 [doi]
• Counteracting Rowhammer by Data AlternationStefan A. Lung, Georgi Gaydadjiev, Said Hamdioui, Mottaqiallah Taouil. 1-6 [doi]
• Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMsPei Yun Lin, Jin-Fu Li. 1-4 [doi]
• Degradation Monitoring Through Software-controlled On-chip Sensors for RISC-VSeyedeh Maryam Ghasemi, Jonas Krautter, Tara Gheshlaghi, Sergej Meschkov, Dennis R. E. Gnad, Mehdi B. Tahoori. 1-6 [doi]
• Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response ModelingTolga Aksoy, Nikhil Sagar Modala, Lakshmanan Balasubramanian, Rubin A. Parekhji, Sule Ozev. 1-6 [doi]
• Transcoders: A Better Alternative To Denoising AutoencodersPushpak Raj Gautam, Alex Orailoglu. 1-4 [doi]
• Training Large Language Models for System-Level Test Program Generation Targeting Non-functional PropertiesDenis Schwachhofer, Peter Domanski, Steffen Becker 0001, Stefan Wagner 0001, Matthias Sauer 0002, Dirk Pflüger, Ilia Polian. 1-4 [doi]
• Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware TestRiccardo Cantoro, Michelangelo Grosso, Iacopo Guglielminetti, Reza Khoshzaban, Matteo Sonza Reorda. 1-4 [doi]
• Keynote 2 - Sustainability and the Outlook of Semiconductor IndustryCheng-Wen Wu, Shi-Yu Huang. 1-2 [doi]
• Hardware-Independent ATE Software for SLTRic Dokken. 1-4 [doi]
• GNN-Based INC and IVC Co-Optimization for Aging MitigationYu-Guang Chen, Hsiu-Yi Yang, Ing-Chao Lin. 1-4 [doi]
• A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256Han Yan, Shuai Chen, Junying Huang, Jing Ye 0001, Huawei Li 0001, Xiaowei Li 0001. 1-4 [doi]
• New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra. 1-10 [doi]
• CGAN-based Automated Fault InjectionTroya Çagil Köylü, Cornelis Christiaan Berg, Praveen Kumar Vadnala. 1-6 [doi]
• Semiconductor Application Fail Root Causes And Secure Test RemedyHeguo Yin, Peter Poechmueller. 1-6 [doi]
• IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICsJuan Suzano, Antoine Chastand, Emanuele Valea, Giorgio Di Natale, Anthony Philippe, Fady Abouzeid, Philippe Roche. 1-6 [doi]
• Detection of Stealthy Bitstreams in Cloud FPGAs using Graph Convolutional NetworksJayeeta Chaudhuri, Krishnendu Chakrabarty. 1-6 [doi]
• Online Detection of Unique Faults in RRAMsHanzhi Xun, Moritz Fieback, Mohammad Amin Yaldagard, Sicong Yuan, Hassen Aziza, Mottaqiallah Taouil, Said Hamdioui. 1-2 [doi]
• Test-Fleet Optimization Using Machine LearningAniruddha Datta, Bhanu Vikas Yaganti, Andrew Dove, Arik Peltz, Krishnendu Chakrabarty. 1-10 [doi]
• Power Analysis Attack Against post-SAT Logic Locking schemesNassim Riadi, Florent Bruguier, Pascal Benoit, Sophie Dupuis, Marie-Lise Flottes. 1-6 [doi]