Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits

Kartik Mohanram, Nur A. Touba. Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. In 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings. pages 433, IEEE Computer Society, 2003. [doi]

Abstract

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