Kartik Mohanram, Nur A. Touba. Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. In 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings. pages 433, IEEE Computer Society, 2003. [doi]
@inproceedings{MohanramT03,
title = {Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits},
author = {Kartik Mohanram and Nur A. Touba},
year = {2003},
url = {http://csdl.computer.org/comp/proceedings/dft/2003/2042/00/20420433abs.htm},
tags = {logic},
researchr = {https://researchr.org/publication/MohanramT03},
cites = {0},
citedby = {0},
pages = {433},
booktitle = {18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings},
publisher = {IEEE Computer Society},
isbn = {0-7695-2042-1},
}