Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits - researchr publication related

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Kartik Mohanram, Nur A. Touba. Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. In 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings. pages 433, IEEE Computer Society, 2003. [doi]

The following publications are possibly variants of this publication:

Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic CircuitsKartik Mohanram, Nur A. Touba. itc 2003: 893-901 [doi]

Masking timing errors on speed-paths in logic circuitsMihir R. Choudhury, Kartik Mohanram. date 2009: 87-92 [doi]

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