Table of Contents

• Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test SetsJennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer. 9-15 [doi]
• ELF-Murphy Data on Defects and Test SetsEdward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra. 16-22 [doi]
• An Experimental Study of N-Detect Scan ATPG Patterns on a ProcessorSrikanth Venkataraman, Srihari Sivaraj, Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo. 23-30 [doi]
• What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?Manish Sharma, Janak H. Patel. 31-36 [doi]
• A Statistical Fault Coverage Metric for Realistic Path Delay FaultsWangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi. 37-42 [doi]
• Delay Defect Screening using Process Monitor StructuresSubhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger. 43-52 [doi]
• Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICsJosep Rius Vázquez, José Pineda de Gyvez. 53-58 [doi]
• On New Current Signatures and Adaptive Test Technique CombinationClaude Thibeault. 59-64 [doi]
• On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector SetSagar S. Sabade, D. M. H. Walker. 65-72 [doi]
• Changing the Scan Enable during ShiftNodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams. 73-78 [doi]
• 3-Stage Variable Length Continuous-Flow Scan Vector Decompression SchemeC. V. Krishna, Nur A. Touba. 79-86 [doi]
• Generating At-Speed Array Fail Maps with Low-Speed ATEMichael R. Nelms, Kevin Gorman, Darren Anand. 87-96 [doi]
• Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its ApplicationDebashis Nayak, Srikanth Venkataraman, Paul J. Thadikaran. 97-102 [doi]
• Yield Analysis of Logic CircuitsDavide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre. 103-108 [doi]
• FPGA Bridging Fault Detection and Location via Differential I{DDQ}Erik Chmelar, Shahin Toutounchi. 109-116 [doi]
• Effects of Bit Line Coupling on the Faulty Behavior of DRAMsZaid Al-Ars, Said Hamdioui, A. J. van de Goor. 117-122 [doi]
• New Test Methodology for Resistive Open Defect Detection in Memory Address DecodersMohamed Azimane, Ananta K. Majhi. 123-128 [doi]
• March iC-: An Improved Version of March C- for ADOFs DetectionLuigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri. 129-138 [doi]
• Multi-Modal Built-In Self-Test for Symmetric MicrosystemsNilmoni Deb, R. D. (Shawn) Blanton. 139-147 [doi]
• A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS DevicesXingguo Xiong, Yu-Liang Wu, Wen-Ben Jone. 148-153 [doi]
• A Multi-Configuration Strategy for an Application Dependent Testing of FPGAsMehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure. 154-170 [doi]
• The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging FaultsPiet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker. 171-178 [doi]
• Sensing temperature in CMOS circuits for Thermal TestingJosep Altet, Antonio Rubio, M. Amine Salhi, J. L. Gálvez, Stefan Dilhaire, Ashish Syal, André Ivanov. 179-184 [doi]
• Detection of Temperature Sensitive Defects Using ZTCEthan Long, W. Robert Daasch, Robert Madge, Brady Benware. 185-192 [doi]
• Planar High Performance Ring GeneratorsGrzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. 193-198 [doi]
• Logic BIST Using Constrained Scan CellsLiyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel. 199-205 [doi]
• BIST Technique by Equally Spaced Test Vector SequencesSalvador Manich, L. García, L. Balado, E. Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras. 206-216 [doi]
• Wafer-level RF Test and DfT for VCO Modulating Transceiver ArchitecuresSule Ozev, Christian Olgaard. 217-222 [doi]
• GHz RF Front-end Bandwidth Time Domain MeasurementQi Wang, Yi Tang, Mani Soma. 223-228 [doi]
• System-level Testing of RF Transmitter Specifications Using Optimized Periodic BitstreamsSoumendu Bhattacharya, Ganesh Srinivasan, Sasikumar Cherubal, Achintya Halder, Abhijit Chatterjee. 229-236 [doi]
• Reducing Embedded SRAM Test Time under Redundancy ConstraintsBaosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian. 237-242 [doi]
• Memory BIST Using ESPXiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk. 243-248 [doi]
• A Methodology for Design and Evaluation of Redundancy Allocation AlgorithmsSamvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian. 249-260 [doi]
• An On-Chip Transfer Function Characterization System for Analog Built-in TestingAlberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio. 261-266 [doi]
• A Scalable On-Chip Jitter Extraction TechniqueChee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang. 267-272 [doi]
• Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise ReferenceSelim Sermet Akbay, Abhijit Chatterjee. 273-290 [doi]
• Defects and Faults in Quantum Cellular Automata at Nano ScaleMehdi Baradaran Tahoori, Mariam Momenzadeh, Jing Huang, Fabrizio Lombardi. 291-296 [doi]
• Generalized Sensitization using Fault TuplesSounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton. 297-303 [doi]
• Fault Simulation Model for i{DDT} Testing: An InvestigationAbhishek Singh, Chintan Patel, Jim Plusquellic. 304-312 [doi]
• A Diversified Memory Built-In Self-Repair Approach for NanotechnologiesMichael Nicolaidis, Nadir Achouri, Lorena Anghel. 313-318 [doi]
• Cost-Driven Selection of Parity TreesSobeeh Almukhaizim, Petros Drineas, Yiorgos Makris. 319-324 [doi]
• Soft Delay Error Effects in CMOS Combinational CircuitsBalkaran S. Gill, Christos A. Papachristou, Francis G. Wolff. 325-334 [doi]
• Testing Systems WirelesslyHans Eberle, Arvinderpal Wander, Nils Gura. 335-340 [doi]
• Design of Wireless Sub-Micron Characterization SystemBrian Moore, Christopher J. Backhouse, Martin Margala. 341-346 [doi]
• Boundary Scan for 5-GHz RF Pins Using LC Isolation NetworksTian-Wei Huang, Pei-Si Wu, Ren-Chieh Liu, Jeng-Han Tsai, Huei Wang, Tzi-Dar Chiueh. 347-354 [doi]
• Hybrid BIST for System-on-a-Chip Using an Embedded FPGA CoreGang Zeng, Hideo Ito. 355-360 [doi]
• Defect-Aware SOC Test SchedulingErik Larsson, Julien Pouget, Zebo Peng. 361-366 [doi]
• Designing Reconfigurable Multiple Scan Chains for Systems-on-ChipMd. Saffat Quasem, Sandeep K. Gupta. 367-376 [doi]
• Prediction of Analog Performance Parameters Using Oscillation Based TestAshwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee. 377-382 [doi]
• An Approach to the Built-In Self-Test of Field Programmable Analog ArraysTiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell. 383-388 [doi]
• Efficient ATPG for Design Validation Based On Partitioned State Exploration HistoriesQingwei Wu, Michael S. Hsiao. 389-405 [doi]