Table of Contents

• Energy minimization for hybrid BIST in a system-on-chip test environmentRaimund Ubar, Tatjana Shchenova, Gert Jervan, Zebo Peng. 2-7 [doi]
• Test scheduling for modular SOCs in an abort-on-fail environmentUrban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen. 8-13 [doi]
• A new SoC test architecture with RF/wireless connectivityDan Zhao, Shambhu J. Upadhyaya, Martin Margala. 14-19 [doi]
• A unified fault model and test generation procedure for interconnect opens and bridgesGang Chen 0011, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker. 22-27 [doi]
• Defective behaviours of resistive opens in interconnect linesDaniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras. 28-33 [doi]
• Testing of resistive opens in CMOS latches and flip-flopsVíctor H. Champac, Antonio Zenteno, José L. Garcia. 34-40 [doi]
• Using dummy bridging faults to define a reduced set of target faultsIrith Pomeranz, Sudhakar M. Reddy. 42-47 [doi]
• Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generationTsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara. 48-53 [doi]
• Path-oriented transition fault test generation considering operating conditionsBharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu. 54-59 [doi]
• Evaluation of signature-based testing of RF/analog circuitsAmir Zjajo, José Pineda de Gyvez. 62-67 [doi]
• Accurate measurement of multi-tone power ratio (MTPR) of ADSL devices using low cost testersGanesh Srinivasan, Sasikumar Cherubal, Pramodchandran N. Variyam, Melese Teklu, C. P. Wang, David Guidry, Abhijit Chatterjee. 68-73 [doi]
• Towards on-line testing of MEMS using electro-thermal excitationFrédérick Mailly, Florence Azaïs, Norbert Dumas, Laurent Latorre, Pascal Nouet. 76-81 [doi]
• Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearitiesAchraf Dhayni, Salvador Mir, Libor Rufer. 82-87 [doi]
• Bias Superposition - An On-Line Test Strategy for a MEMS Based Conductivity SensorCarl Jeffrey, Zhou Xu, Andrew Richardson. 88-93 [doi]
• DOT: new deterministic defect-oriented ATPG toolJaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz. 96-101 [doi]
• Logic circuit testing for transient faultsSmita Krishnaswamy, Igor L. Markov, John P. Hayes. 102-107 [doi]
• A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe pointsArijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy. 108-113 [doi]
• Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterizationLuigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan. 116-121 [doi]
• Automatic March tests generation for static and dynamic faults in SRAMsAlfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 122-127 [doi]
• A programmable time measurement architecture for embedded memory characterizationMatthew Collins, Bashir M. Al-Hashimi, Neil Ross. 128-133 [doi]
• Multiple errors produced by single upsets in FPGA configuration memory: a possible solutionMatteo Sonza Reorda, Luca Sterpone, Massimo Violante. 136-141 [doi]
• Fault collapsing for flash memory disturb faultsMohammad Gh. Mohammad, Laila Terkawi. 142-147 [doi]
• Low power embedded DRAMs with high quality error correcting capabilitiesPhilipp Öhler, Sybille Hellebrand. 148-153 [doi]
• Design validation of behavioral VHDL descriptions for arbitrary fault modelsFei Xin, Maciej J. Ciesielski, Ian G. Harris. 156-161 [doi]
• Coverage of formal properties based on a high-level fault model and functional ATPGFranco Fummi, Graziano Pravadelli, Franco Toto. 162-167 [doi]
• Built-in self-test of molecular electronics-based nanofabricsZhanglei Wang, Krishnendu Chakrabarty. 168-173 [doi]
• Convolutional compaction-driven diagnosis of scan failuresGrzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang. 176-181 [doi]
• Stuck-open fault diagnosis with stuck-at modelXinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud. 182-187 [doi]
• Test control for secure scan designsDavid Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. 190-195 [doi]
• Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channelsAdam B. Kinsman, Nicola Nicolici. 196-201 [doi]
• Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCsPaolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda. 202-207 [doi]
• The anatomy of nanometer timing failuresChuck Hawkins, Jaume Segura. 210-215 [doi]
• From embedded test to embedded diagnosisHans-Joachim Wunderlich. 216-221 [doi]
• Test for low cost CMOS image sensorsPeter Maxwell. 222 [doi]
• Testing of MEMS-based microsystemsHans G. Kerkhoff. 223-228 [doi]