Abstract is missing.
- Combined DRAM and logic chip for massively parallel systemsPeter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter. 4-16 [doi]
- Silicon VLSI processing architectures incorporating integrated optoelectronic devicesHuy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst. 17-27 [doi]
- Abacus: a 1024 processor 8 ns SIMD arrayM. Bolotski, T. Simon, C. Vieri, R. Amirtharajah, Thomas F. Knight Jr.. 28-41 [doi]
- Automatic synthesis of gate-level timed circuits with choiceChris J. Myers, Tomas Rokicki, Teresa H. Y. Meng. 42-58 [doi]
- Algorithms for the optimal state assignment of asynchronous state machinesRobert M. Fuhrer, Bill Lin, Steven M. Nowick. 59-75 [doi]
- Low latency self-timed flow-through FIFOsErik Brunvand. 76-90 [doi]
- High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chipsJae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews. 91-107 [doi]
- Bit-serial bidirectional A/D/A conversioGert Cauwenberghs. 108-120 [doi]
- Dynamic CMOS circuit techniques for delay and power reduction in parallel adders Hans Lindkvist, Per Andersson. 121-130 [doi]
- A technique for high-speed, fine-resolution pattern generation and its CMOS implementationGary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III. 131-149 [doi]
- Array-of-arrays architecture for parallel floating point multiplicationH. Dhanesha, K. Falakshahi, Mark Horowitz. 150-157 [doi]
- A multi-sender asynchronous extension to the AER protocolJohn Lazzaro, John Wawrzynek. 158-171 [doi]
- Recursive layout generationLouis Monier, Ramsey W. Haddad, Jeremy Dion. 172-184 [doi]
- HAL: heuristic algorithms for layout synthesisSanjay Rekhi, J. Donald Trotter. 185-199 [doi]
- Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectricsX. Cai, Keith Nabors, Jacob White. 200-213 [doi]
- Standard CMOS active pixel image sensors for multimedia applicationsAlex G. Dickinson, Bryan D. Ackland, El-Sayed Eid, David A. Inglis, Eric R. Fossum. 214-224 [doi]
- A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retinaAndreas G. Andreou, Kwabena Boahen. 225-240 [doi]
- Analog VLSI circuits for manufacturing inspectionTonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth. 241-257 [doi]
- OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositionsHuy Nguyen, Abhijit Chatterjee. 258-271 [doi]
- Code density optimization for embedded DSP processors using data compression techniquesStan Y. Liao, Srinivas Devadas, Kurt Keutzer. 272-285 [doi]
- Systematic objective-driven computer architecture optimizationTimothy J. Stanley, Trevor N. Mudge. 286-303 [doi]
- Low-latency plesiochronous data retimingLarry R. Dennison, William J. Dally, Thucydides Xanthopoulos. 304-315 [doi]
- Distributed synchronous clockingGill A. Pratt, John Nguyen. 316-330 [doi]
- Single-transistor transparent-latch clockingKei-Yong Khoo, Alan N. Willson Jr.. 331-341 [doi]
- On the performance of level-clocked circuitsCarl Ebeling, Brian Lockyear. 342-357 [doi]
- Quasi-algebraic decompositions of switching functionsTed Stanion, Carl Sechen. 358-367 [doi]
- Efficient retiming under a general delay modelKumar N. Lalgudi, Marios C. Papaefthymiou. 368-382 [doi]
- An evaluation of bipartitioning techniquesScott Hauck, Gaetano Borriello. 383-403 [doi]
- Non-dissipative rail drivers for adiabatic circuitsS. G. Younis, Thomas F. Knight Jr.. 404-414 [doi]
- Energy recovery for low-power CMOSWilliam C. Athas, Nestoras Tzartzanis. 415-429 [doi]
- Optimization of combinational and sequential logic circuits for low power using precomputationJosé Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh. 430-444 [doi]