Albert van der Werf, B. T. McSweeney, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh. Hierarchical Retiming Including Pipelining. In Arne Halaas, Peter B. Denyer, editors, VLSI 91, Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration, Edinburgh, Scotland, 20-22 August, 1991. Volume A-1 of IFIP Transactions, pages 451-460, North-Holland, 1991.
Abstract is missing.