Abstract is missing.
- Approximation of critical area of ICs with simple parameters extracted from the layoutFrederic Duvivier, M. Rivier. 1-9 [doi]
- AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layoutIgor Bubel, Wojciech Maly, Thomas Waas, Pranab K. Nag, Hans Hartmann, Doris Schmitt-Landsiedel, Susanne Griep. 10-18 [doi]
- Hierarchical extraction of critical area for shorts in very large ICsPranab K. Nag, Wojciech Maly. 19-27 [doi]
- Hierarchical critical area extraction with the EYE toolGerard A. Allan, Anthony J. Walton. 28-36 [doi]
- Wafer-scale integration defect avoidance tradeoffs between laser links and Omega network switchingGlenn H. Chapman, D. E. Bergen, K. Fang. 37-45 [doi]
- The effect of spot defects on the parametric yield of long interconnection linesIsrael A. Wagner, Israel Koren. 46-54 [doi]
- Critical area extraction of extra material soft faultsGerard A. Allan, Anthony J. Walton. 55-62 [doi]
- Switch level hot-carrier reliability enhancement of VLSI circuitsAurobindo Dasgupta, Ramesh Karri. 63-71 [doi]
- A model for the evaluation of fault tolerance in the FERMI systemAnna Antola, Luca Breveglieri. 72-80 [doi]
- Efficient algorithms for analyzing and synthesizing fault-tolerant datapathsRagini Narasimhan, Daniel J. Rosenkrantz, S. S. Ravi. 81-89 [doi]
- Bit-modular defect/fault-tolerant convolversLuigi Dadda, Vincenzo Piuri. 90-98 [doi]
- A Channel-Constrained Reconfiguration Approach for Processing ArraysMariagiovanna Sami, Fausto Distante, Renato Stefanelli. 99-107 [doi]
- Reconfigurable architectures for mesh-arrays with PE and link faultsItsuo Takanami, Tadayoshi Horita. 108-116 [doi]
- Totally defect-tolerant arrays capable of quick broadcastingNobuo Tsuda, Tsutomu Ishikawa, Yukihiro Nakamura. 117-125 [doi]
- ADTS: an array defect-tolerance scheme for wafer scale gate arraysAdit D. Singh. 126-136 [doi]
- An improved approach to fault tolerant rank order filtering on a SIMD mesh processorJai-Hoon Kim, Fabrizio Lombardi, Nitin H. Vaidya. 137-145 [doi]
- Yield projection from defect monitors: the influence of gross defects [BiCMOS process]Neil Harrison. 146-154 [doi]
- Accurate yield estimation of circuits with redundancyDinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly. 155-163 [doi]
- Using defect density modelling to drive the optimisation of circuit layout, maximising yieldM. Baxter, D. Muir. 164-172 [doi]
- Layer assignment for yield enhancementZhan Chen, Israel Koren. 173-180 [doi]
- Analyzing and improving delay defect tolerance in pipelined combinational circuitsDavid Wessels, Jon C. Muzio. 181-188 [doi]
- Cost analysis of a new algorithmic-based soft-error tolerant architectureYves Blaquière, Gabriel Gagné, Yvon Savaria, Claude Évéquoz. 189-197 [doi]
- Efficient time redundancy for error correcting inner-product units and convolversYuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.. 198-206 [doi]
- A study of time redundant fault tolerance techniques for superscalar processorsManoj Franklin. 207-215 [doi]
- Repair algorithms for mirrored disk systemsHannu Kari, Heikki Saikkonen, Sungsoo Kim, Fabrizio Lombardi. 216-224 [doi]
- A row-based FPGA for single and multiple stuck-at fault detectionXiao-Tao Chen, Wei-Kang Huang, Fabrizio Lombardi, Xiao Sun 0002. 225-233 [doi]
- Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosisStephanie R. Goldberg, Shambhu J. Upadhyaya. 234-242 [doi]
- FFT-based test of a yield monitor circuitClaude Thibeault, A. Payeur. 243-251 [doi]
- Design of defect-tolerant scan chains for MCMs with an active substrateP. Brahic, Régis Leveugle, Gabriele Saucier. 252-260 [doi]
- Characterization and analysis of errors in circuit testThomas A. Ziaja, Earl E. Swartzlander Jr.. 261-268 [doi]
- Self-checking FSMs based on a constant distance state encodingCristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto. 269-277 [doi]
- Constructions of the SbEC-DbED and DbEC codes, and their applicationsGuilang Feng, Sihai Xiao, Xiaofa Shi, T. R. N. Rao. 278-286 [doi]
- Novel Berger code checkerCecilia Metra, Michele Favalli, Bruno Riccò. 287-295 [doi]
- Single fault masking logic designs with error correcting codesJien-Chung Lo. 296 [doi]