Nobuo Tsuda - researchr alias

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Viewing Publication 1 - 13 from 13

2002

Configurable PC Clusters Using a Hierarchical Complete-Connection-Based Switching NetworkNobuo Tsuda. prdc 2002: 153-162 [doi]

2001

ABL-Tree: A Constant Diameter Interconnection Network for Reconfigurable Processor Arrays Capable of Distributed Communication Nobuo Tsuda. dft 2001: 143-148 [doi]

2000

Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node ColoringNobuo Tsuda. TC, 49(5):431-442, 2000. [doi]

Fault-Tolerant Ring- and Toroidal Mesh-Connected Processor Arrays Able to Enhance Emulation of HypercubesNobuo Tsuda. dft 2000: 222-230 [doi]

Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct ReplacementNobuo Tsuda, Tatsuyuki Shimizu. ispan 2000: 24-29 [doi]

1997

Fault-Tolerant Hierarchical Interconnection Networks Constructed by Additional Bypass Linking with Graph-Node ColoringNobuo Tsuda. dft 1997: 227-233 [doi]

1996

Fault-Tolerant Shuffle-Exchange and de Bruijn Networks Capable of Quick BroadcastingNobuo Tsuda. dft 1996: 231-239 [doi]

1995

A Rule-Embedded Neural-Network and Its Effectiveness in Pattern Recognition with III-Posed ConditionsMina Maruyama, Nobuo Tsuda, Kiyoshi Nakabayashi. ieicet, 78-D(2):152-162, 1995. [doi]

Totally defect-tolerant arrays capable of quick broadcastingNobuo Tsuda, Tsutomu Ishikawa, Yukihiro Nakamura. dft 1995: 117-125 [doi]

1993

Hierarchical redundancy for two-dimensional orthogonal arrays using defect-tolerant replacement circuitsNobuo Tsuda. scjapan, 24(2):22-34, 1993. [doi]

Defect- and fault-tolerant static ram module designs based on parity checking and automatic testingNobuo Tsuda. scjapan, 24(2):1-10, 1993. [doi]

Hierarchical redundancy for array-structure wsisNobuo Tsuda. scjapan, 24(7):13-30, 1993. [doi]

1989

A Compact Multiway Merge Sorter using Linear-Array ComparatorsTetsuji Satoh, Hideaki Takeda, Nobuo Tsuda. fodo 1989: 223-227

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