Tsutomu Ishikawa - researchr alias

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Viewing Publication 1 - 18 from 18

2023

2021

2020

Highly Reliable and Compact InP-Based In-Phase and Quadrature Modulators for Over 400 Gbit/s Coherent Transmission SystemsHajime Tanaka, Tsutomu Ishikawa, Takashi Kitamura, Masataka Watanabe, Ryuji Yamabi, Ryo Yamaguchi, Naoya Kono, Takehiko Kikuchi, Morihiro Seki, Tomokazu Katsuyama, Mitsuru Ekawa, Hajime Shoji. ieicetc, 103-C(11):661-668, 2020. [doi]

2019

Study on the optical damage mechanism of InP IQ modulators using a step stress testHajime Tanaka, Tsutomu Ishikawa, Mitsuru Ekawa. ps 2019: 1-3 [doi]

2006

Inference Scheme for Order-Sorted Logic Using Noun Phrases with Variables as SortsMasaki Kitano, Seikoh Nishita, Tsutomu Ishikawa. micai 2006: 49-58 [doi]

2002

A mechanism for inferring approximate solutions under incomplete knowledge based on rule similarityViet Ha Nguyen, Tsutomu Ishikawa, Akinori Abe. scjapan, 33(9):78-89, 2002. [doi]

1997

Stock Price Prediction Using Prior Knowledge and Neural NetworksKazuhiro Kohara, Tsutomu Ishikawa, Yoshimi Fukuhara, Yukihiro Nakamura. isafm, 6(1):11-22, 1997. [doi]

1995

Hypercube Multiprocessors with Bus Connections for Improving Communication PerformanceTsutomu Ishikawa. TC, 44(11):1338-1344, 1995.

Viewpoint-Based Measurement of Semantic Similarity between WordsKaname Kasahara, Kazumitsu Matsuzawa, Tsutomu Ishikawa, Tsukasa Kawaoka. aistats 1996: 433-442 [doi]

Totally defect-tolerant arrays capable of quick broadcastingNobuo Tsuda, Tsutomu Ishikawa, Yukihiro Nakamura. dft 1995: 117-125 [doi]

1994

Bypass Strategy in Hypercube Multiprocessors by adding Bus ConnectionsTsutomu Ishikawa. parle 1994: 226-237

1993

Optimal parallel back-propagation schemes for mesh-connected and bus-connected multiprocessorsTakashi Yukawa, Tsutomu Ishikawa. icnn 1993: 1748-1753 [doi]

1991

Hypercube Architecture with Bus Connections for Improving Communication EfficiencyTsutomu Ishikawa. scjapan, 22(5):21-29, 1991. [doi]

1990

Universal Fault-Tolerant Hypercube Architecture without a Switching MechanismTsutomu Ishikawa. scjapan, 21(3):57-65, 1990. [doi]

Presto: A Bus-Connected Multiprocessor for a Rete-Based Production SystemHideo Kikuchi, Takashi Yukawa, Kazumitsu Matsuzawa, Tsutomu Ishikawa. conpar 1990: 63-74

1986

Hierarchical Array Processor (HAP) Featuring High Reliability and High System PerformanceTsutomu Ishikawa, Shigeharu Momoi, Shigeo Shimada, Yoshio Ogawa. icpp 1986: 293-300

Hierarchical Array Processor System (HAP)Shigeharu Momoi, Shigeo Shimada, Masamitsu Kobayashi, Tsutomu Ishikawa. conpar 1986: 311-318

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