Abstract is missing.
- The Teramac Custom Computer: Extending the Limits with Defect ToleranceW. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider. 2-10 [doi]
- Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arraysGlenn H. Chapman, Benoit Dufort. 11-20 [doi]
- Extraction of critical areas for opens in large VLSI circuitsCharles H. Ouyang, Witold A. Pleskacz, Wojciech Maly. 21-29 [doi]
- Fatal Fault Probability Prediction for Array Based DesignsDinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker. 30-38 [doi]
- Yield Prediction by Sampling with the EYES ToolGerard A. Allan, Anthony J. Walton. 39-47 [doi]
- Application of a Survey Sampling Critical Area Computation Tool in a Manufacturing EnvironmentFrederic Duvivier, Gerard A. Allan. 48-52 [doi]
- Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip CachesDimitris Nikolos, Haridimos T. Vergos, Antonis Vazaios, Spyros Voulgaris. 53-58 [doi]
- Integration of DFM Techniques and Design AutomationThomas G. Waring, Gerard A. Allan, Anthony J. Walton. 59-67 [doi]
- Trade-offs between yield and reliability enhancement [VLSI]Arunshankar Venkataraman, Israel Koren. 68-76 [doi]
- Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel RoutingZhan Chen, Israel Koren. 77-85 [doi]
- Detection of an antenna effect in VLSI designsWojciech Maly, Charles H. Ouyang, Subhendra Ghosh, Sury Maturi. 86-95 [doi]
- Integrated Approach for Circuit and Fault Extraction of VLSI CircuitsFernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. 96-104 [doi]
- Layout-driven detection of bridge faults in interconnectsTong Liu, Xiao-Tao Chen, Fabrizio Lombardi, José Salinas. 105-113 [doi]
- Test Sequence Generation for Realistic Faults in CMOS ICs Based on Standard Cell LibraryPeilin Song, Jien-Chung Lo. 114-123 [doi]
- Impact of Physical Defects on the Electrical Working of Embedded DRAM with 0.35B5m Design RulesPascal Bichebois. 124-130 [doi]
- A Statistical Parametric and Probe Yield Analysis MethodologyAllan Y. Wong. 131-139 [doi]
- The Prediction of Circuit Performance Variations for Deep Submicron CMOS ProcessesThomas Gneiting, Ian P. Jalowiecki. 140-148 [doi]
- Maximum Likelihood Estimation for Yield AnalysisF. Joel Ferguson, Jianlin Yu. 149-158 [doi]
- Comprehensive Modeling of VLSI TestThomas A. Ziaja, Earl E. Swartzlander Jr.. 159-167 [doi]
- Modeling Quality Reduction of Multichip Module Systems due to Uneven Fault-Coverage and Imperfect DiagnosisNohpill Park, Fabrizio Lombardi, Sungsoo Kim. 168-176 [doi]
- Error Identification and Data Retrieval in Signature Analysis based Data CompactionXiaoling Sun, Wes Tutak. 177-184 [doi]
- Experimental Results from Iddf TestingClaude Thibeault, A. Payeur. 185-194 [doi]
- A unified approach for off-line and on-line testing of VLSI systemsParag K. Lala, S. Yang, Fadi Busaba. 195-203 [doi]
- Compact and Highly Testable Error Indicator for Self-Checking CircuitsCecilia Metra, Michele Favalli, Bruno Riccò. 204-212 [doi]
- Tree Checkers for Applications with Low Power-Delay RequirementsCecilia Metra, Michele Favalli, Bruno Riccò. 213-220 [doi]
- A Parametric Design of a Built-in Self-Test FIFO Embedded MemoryStefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Gabriel de Blasio, M. Ferloni, Franco Fummi, Donatella Sciuto. 221-230 [doi]
- Fault-Tolerant Shuffle-Exchange and de Bruijn Networks Capable of Quick BroadcastingNobuo Tsuda. 231-239 [doi]
- Fault tolerant Newton-Raphson dividers using time shared TMRW. Lynn Gallagher, Earl E. Swartzlander Jr.. 240-248 [doi]
- Balancing of Fault Tolerance in the New Version of the FERMI Channel Chip: a Functional EvaluationAnna Antola, Luca Breveglieri. 249-257 [doi]
- Fault detection and fault tolerance issues at CMOS level through AUED encodingCristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli. 258-267 [doi]
- Optimizing High-Level Synthesis for Self-Checking Arithmetic CircuitsAnna Antola, Vincenzo Piuri, Mariagiovanna Sami. 268-276 [doi]
- Redundant Faults in TSC Networks: Definition and RemovalCristiana Bolchini, Fabio Salice, Donatella Sciuto. 277-285 [doi]
- Reliable Logic Circuits with Byte Error Control Codes: A Feasibility StudyJien-Chung Lo, Masato Kitakami, Eiji Fujiwara. 286-294 [doi]
- Configurable Spare Processors: A New Approach to System Level-Fault ToleranceKyosun Kim, Ramesh Karri, Miodrag Potkonjak. 295-303 [doi]
- ROM-Based Synthesis of Fault-Tolerant ControllersX. Wendling, R. Rochet, Régis Leveugle. 304-309 [doi]
- Implementing Fault Injection and Tolerance Mechanisms in Multiprocessor SystemsDaniel Audet, N. Gagnon, Yvon Savaria. 310-317 [doi]
- Recovery Schemes for Mesh Arrays Utilizing Dedicated SparesStephanie R. Goldberg, Shambhu J. Upadhyaya, W. Kent Fuchs. 318-326 [doi]
- KITE: a behavioural approach to fault-tolerance in FPGA-based systemsGiovanni A. Mojoli, Davide Salvi, M. G. Sami, Giacomo R. Sechi, Renato Stefanelli. 327-334 [doi]
- Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faultsTadayoshi Horita, Itsuo Takanami. 335 [doi]