Table of Contents

• Resource-efficient regular expression matching architecture for text analyticsKubilay Atasu. 1-8 [doi]
• Map-reduce processing of k-means algorithm with FPGA-accelerated computer clusterYuk-Ming Choi, Hayden Kwok-Hay So. 9-16 [doi]
• Adaptive scalable SVD unit for fast processing of large LSE problemsInaki Bildosola, Unai Martinez-Corral, Koldo Basterretxea. 17-24 [doi]
• SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISCMichael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Luca Benini, Beat Muheim, Hubert Kaeslin. 25-29 [doi]
• Customizable coarse-grained energy-efficient reconfigurable packet processing architectureMohammad Badawi, Ahmed Hemani, Zhonghai Lu. 30-35 [doi]
• Low latency FPGA acceleration of market data feed arbitrationStewart Denholm, Hiroaki Inoue, Takashi Takenaka, Tobias Becker, Wayne Luk. 36-40 [doi]
• Sum-of-product architectures computing just rightFlorent de Dinechin, Matei Istoan, Abdelbassat Massouri. 41-47 [doi]
• Pipelined modular multiplier supporting multiple standard prime fieldsHamad Alrimeih, Daler N. Rakhmatov. 48-56 [doi]
• RNS modular multiplication through reduced base extensionsKarim Bigou, Arnaud Tisserand. 57-62 [doi]
• On the computation of the reciprocal of floating point expansions using an adapted Newton-Raphson iterationMioara Joldes, Jean-Michel Muller, Valentina Popescu. 63-67 [doi]
• Polar baseband receiver for low-end WLANAmro Altamimi, Daler N. Rakhmatov, Michael McGuire. 68-69 [doi]
• Design of a 2D graphics front-end rendering processorYun-Nan Chang, Ting-Chi Tong. 70-71 [doi]
• Performance modeling of virtualized custom logic computationsMichael J. Hall, Roger D. Chamberlain. 72-73 [doi]
• HICore1: "Safety on a chip" turnkey solution for industrial controlAli Hayek, Bashier Machmur, Michael Schreiber, Josef Börcsök, Stefan Golz, Mario Epp. 74-75 [doi]
• A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon eraMehdi Modarressi, Hamid Sarbazi-Azad. 76-77 [doi]
• Randomized windows for secure scalar multiplication on elliptic curvesSimon Pontie, Paolo Maistri. 78-79 [doi]
• Virtual semi-concurrent self-checking for heterogeneous MPSoC architecturesMariagiovanna Sami, Gianluca Palermo. 80-81 [doi]
• Distributed synchronization for message-passing based embedded multiprocessorsHao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Guanyu Zhu. 82-83 [doi]
• Performance modeling for highly-threaded many-core GPUsLin Ma, Roger D. Chamberlain, Kunal Agrawal. 84-91 [doi]
• Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA systemHeiner Giefers, Raphael Polig, Christoph Hagleitner. 92-99 [doi]
• Coordinated and adaptive power gating and dynamic voltage scaling for energy minimizationNathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak. 100-107 [doi]
• A case against small data types in GPGPUsAhmad Lashgar, Amirali Baniasadi. 108-113 [doi]
• He-P2012: Architectural heterogeneity exploration on a scalable many-core platformFrancesco Conti, Chuck Pilkington, Andrea Marongiu, Luca Benini. 114-120 [doi]
• Function-Level Processor (FLP): Raising efficiency by operating at function granularity for market-oriented MPSoCHamed Tabkhi, Robert Bushey, Gunar Schirner. 121-130 [doi]
• Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chipWaqar Hussain, Roberto Airoldi, Henry Hoffmann, Tapani Ahonen, Jari Nurmi. 131-138 [doi]
• Secure interrupts on low-end microcontrollersRuan de Clercq, Frank Piessens, Dries Schellekens, Ingrid Verbauwhede. 147-152 [doi]
• On the characterization of OpenCL dwarfs on fixed and reconfigurable platformsKonstantinos Krommydas, Wu-chun Feng, Muhsen Owaida, Christos D. Antonopoulos, Nikolaos Bellas. 153-160 [doi]
• Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applicationsEdoardo Paone, Davide Gadioli, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano. 161-168 [doi]
• Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformationsThomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin Martin, Philippe Coussy. 169-172 [doi]
• Domain-specific augmentations for High-Level SynthesisMoritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal. 173-177 [doi]
• Virtual science on the move: Interactive access to simulations on supercomputersJunyi Han, Robert Haines, Adel Salhli, John Martin Brooke, Bruce D'Amora, Bob Danani. 178-179 [doi]
• A practical network intrusion detection system for inline FPGAs on 10GbE network adaptersKeerthan Jaic, Melissa C. Smith, Nilim Sarma. 180-181 [doi]
• An approach of processor core customization for stencil computationYanhua Li, Youhui Zhang, Jianfeng Yang, Wayne Luk, Guangwen Yang, Weimin Zheng. 182-183 [doi]
• SWAPHI: Smith-waterman protein database search on Xeon Phi coprocessorsYongchao Liu, Bertil Schmidt. 184-185 [doi]
• A scalable and compact systolic architecture for linear solversKevin Shen-Hoong Ong, Suhaib A. Fahmy, Keck Voon Ling. 186-187 [doi]
• Efficient and scalable CGRA-based implementation of Column-wise Givens RotationZoltán Endre Rákossy, Farhad Merchant, Axel Acosta Aponte, S. K. Nandy, Anupam Chattopadhyay. 188-189 [doi]
• Bandwidth compression of multiple numerical data streams for high performance custom computingTomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto. 190-191 [doi]
• A customized GPU acceleration of the princeton ocean modelShizhen Xu, Xiaomeng Huang, Yan Zhang, Yong Hu, Guangwen Yang. 192-193 [doi]
• Pipelined reconfigurable accelerator for ordinal pattern encodingCe Guo, Wayne Luk, Stephen Weston. 194-201 [doi]
• Energy efficient canonical huffman encodingJanarbek Matai, Joo-Young Kim, Ryan Kastner. 202-209 [doi]
• Flexible multistandard FEC processor design with ASIP methodologyZhenzhi Wu, Dake Liu. 210-218 [doi]
• Energy-efficient gear-shift LDPC decodersKevin Cushon, Saied Hemati, Shie Mannor, Warren J. Gross. 219-223 [doi]
• Exploring DMA-assisted prefetching strategies for software caches on multicore clustersChristian Pinto, Luca Benini. 224-231 [doi]
• A compression-based morphable PCM architecture for improving resistance drift toleranceMajid Jalili, Hamid Sarbazi-Azad. 232-239 [doi]
• PVMC: Programmable Vector Memory ControllerTassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero. 240-247 [doi]
• Understanding the design space of DRAM-optimized hardware FFT acceleratorsBerkin Akin, Franz Franchetti, James C. Hoe. 248-255 [doi]
• Quality-aware video decoding on thermally-constrained MPSoC platformsDeepak Gangadharan, Jürgen Teich, Samarjit Chakraborty. 256-263 [doi]
• Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s eraJoao Andrade, Frederico Pratas, Gabriel Falcão, Vítor Manuel Mendes da Silva, Leonel Sousa. 264-269 [doi]