Table of Contents

• On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency islandSong Jin, Songwei Pei, Yinhe Han, Huawei Li. 1-4 [doi]
• An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development supportHsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang Jain, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee. 1-4 [doi]
• Lifetime-aware LRU promotion policy for last-level cacheHong-Yi Wu, Chien-Chih Chen, Hsiang-Jen Tsai, Yin-Chi Peng, Tien-Fu Chen. 1-4 [doi]
• IC design challenges and opportunities for advanced process technologyHsien-Hsin S. Lee. 1-2 [doi]
• Improve transition fault diagnosability via observation point insertionCheng-Hung Wu, Yi-Da Wang, Kuen-Jong Lee. 1-4 [doi]
• Low-power gated clock tree optimization for three-dimensional integrated circuitsYu-chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin. 1-4 [doi]
• An impact of process variation on supply voltage dependence of logic path delay variationShinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera. 1-4 [doi]
• Identify problematic layout patterns through volume diagnosisWu-Tung Cheng. 1 [doi]
• System-level test coverage prediction by structural stress test data miningBing-Yang Lin, Cheng-Wen Wu, Harry H. Chen. 1-4 [doi]
• Drivers and aspects of 2.5/3D integration as a potential game-changerCarl Engblom. 1 [doi]
• A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systemsLiang-Yu Huang, Chia-Yi Wu, Chun-Yi Liu, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou. 1-4 [doi]
• ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arraysYi-Hang Chen, Yang Chen, Juinn-Dar Huang. 1-4 [doi]
• Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMsShyue-Kung Lu, Shu Ling Lin, Hao-Wei Lin, Masaki Hashizume. 1-4 [doi]
• An effective photoplethysmography signal processing system based on EEMD methodJia-Ju Liao, Shang-Yi Chuang, Chia-Ching Chou, Chia-Chi Chang, Wai-Chi Fang. 1-4 [doi]
• An in-pixel equalizer with kTC noise cancellation and FPN reduction for time-of-flight CMOS image sensorZheng-wei Huang, Chin-Fong Chiu, Chih-Cheng Hsieh. 1-4 [doi]
• Clock-domain-aware test for improving pattern compressionKun-Han Tsai, Janusz Rajski. 1-4 [doi]
• Integrating aging aware timing analysis into a commercial STA toolShushanik Karapetyan, Ulf Schlichtmann. 1-4 [doi]
• Current source model of combinational logic gates for accurate gate-level circuit analysis and timing analysisKai Chen, Young-Hwan Kim. 1-4 [doi]
• An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiverPing-Yuan Tsai, Yu-Yun Chang, Shu-Yu Hsu, Chen-Yi Lee. 1-4 [doi]
• Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applicationsChieh-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang. 1-4 [doi]
• A 60-dB DR PGA with DC-offset calibration for short-distance wireless receiverXiaokun Zhao, Zheng Song, Baoyong Chi. 1-4 [doi]
• Constraints and design approaches in analog ICs forlmplantable medical devicesFernando Silveira, Julian Oreggioni, Pablo Castro-Lisboa. 1-4 [doi]
• TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defectsAng-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, James Chien-Mo Li. 1-4 [doi]
• An addressable UHF EPCGlobal Class1 Gen2 Sensor IC for wireless IOP monitoring on contact lensJin-Chern Chiou, Shun-Hsi Hsu, Cheng-Kai Kuei, Tsung-Wei Wu. 1-4 [doi]
• Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC unitsSunil Dutt, Anshu Chauhan, Sukumar Nandi, Gaurav Trivedi. 1-4 [doi]
• A power-efficient circuit design of feed-forward FxLMS active noise cancellation for in-ear headphonesHong-Son Vu, Kuan-Hung Chen, Shih-Feng Sun, Tien-Mau Fong, Che-Wei Hsu, Lei Wang. 1-4 [doi]
• Cost challenges on the way to the Internet of ThingsWalden C. Rhines. 1 [doi]
• Design-technology innovations enabling differentiation in emerging applicationsSubramani Kengeri. 1 [doi]
• A wireless power transmission subsystem with capacitor-less high PSR LDO and thermal protection mechanism for artificial retina applicationYen-Fu Chen, Kea-Tiong Tang. 1-4 [doi]
• Adaptive granularity and coordinated management for timely prefetching in multi-core systemsChia-Jung Chang, Yin-Chi Peng, Chien-Chih Chen, Tien-Fu Chen, Pen-Chung Yew. 1-4 [doi]
• A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulatorYanfeng Li, Yutao Liu, Woogeun Rhee, Zhihua Wang. 1-4 [doi]
• Power and sensor semiconductors driving automotive applicationsHans Stork. 1 [doi]
• Hydrogel-based microdevicesYao-Joe Yang. 1 [doi]
• A dual-edge sampling CES delay-locked loop based clock and data recovery circuitsJih Ren Goh, Yen-Long Lee, Soon-Jyh Chang. 1-4 [doi]
• Specialty technology for loTGene Li. 1 [doi]
• A 3D hand tracking design for gesture control in complex environmentsPo-Yu Chien, Yuan-Hsiang Miao, Jiun-In Guo. 1-4 [doi]
• Prospect of embedded non-volatile memory in the smart societyTadaaki Yamauchi. 1-2 [doi]
• A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applicationsAn-Tia Xiao, Shiang-Ren Yang, Yuan-Hsiang Miao, Ching-Hwa Cheng, Jiun-In Guo. 1-4 [doi]
• Efficient highly-parallel turbo decoder for 3GPP LTE-AdvancedJing-Shiun Lin, Ming-Der Shieh, Chung-Yen Liu, Der-Wei Yang. 1-4 [doi]
• Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraintJai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan. 1-4 [doi]
• An algorithmic error-resilient scheme for robust LDPC decodingHuai-Ting Li, Ding-Yuan Lee, Kun-Chih Chen, An-Yeu Andy Wu. 1-4 [doi]
• Circuit and system design for robotic flying vehiclesDavid M. Brooks. 1 [doi]
• A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOSHugo Cruz, Hong-Yi Huang, Shueen-Yu Lee, Ching-Hsing Luo. 1-4 [doi]
• A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizerChan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin. 1-4 [doi]
• A 1 Mb/s-40 Mb/s human body channel communication transceiverChing-Che Chung, Chi-Tung Chang, Chih-Yu Lin. 1-4 [doi]
• Evaluation methods of computer memory systemShih-Lien Lu. 1-4 [doi]
• SoC test integration platformAugusli Kifli, Kun-Cheng Wu. 1-2 [doi]
• Electro-thermal modeling of a Rogowski coil sensor systemJuan Sebastian Rodriguez Estupinan, Alain Vachoux, Joris Pascal. 1-4 [doi]
• A pliable and batteryless real-time ECG monitoring system-in-a-patchC. C. Wu, W.-C. Kuo, H. J. Wang, Y. C. Huang, Y. H. Chen, Y.-Y. Chou, S.-A. Yu, S.-S. Lu. 1-4 [doi]
• Design and VLSI implementation of novel pre-screening and simplified sorting based K-best detection for MIMO systemsJheng-Jhan He, Chih-Peng Fan. 1-4 [doi]
• Semiconductor specialty technologies in IOT eraHsiao-Chin Tuan. 1 [doi]
• Design of near-threshold microcontroller for wireless sensing applicationsWei-Xiang Tang, Keng-Yu Lin, Po-Han Haung. 1-4 [doi]
• An embedded ReRAM using a small-offset sense amplifier for low-voltage operationsAlbert Lee, Chien-Chen Lin, Ting-Chin Yang, Meng-Fan Chang. 1-4 [doi]
• All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reductionYi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang. 1-4 [doi]
• Low-power IC design challengeCheng-Chih Mao. 1 [doi]
• Active ESD protection for input transistors in a 40-nm CMOS processFederico A. Altolaguirre, Ming-Dou Ker. 1-4 [doi]
• IoT evolution - By crossing application domainsPeter Hsieh. 1 [doi]
• A 0.6V, 1.3GHz dynamic comparator with cross-coupled latchesBo-Jyun Kuo, Bo-Wei Chen, Chia-Ming Tsai. 1-4 [doi]
• A low-noise high-efficient buck converter with noise-shaping techniqueJiann-Jong Chen, Ping-Hua Wu, Ta-Wei Chao, Yi-Tsen Ku, Yuh-Shyan Hwang, Cheng-Chieh Yu. 1-4 [doi]
• Reusable and flexible verification methodology from architecture to RTL designWen-Ping Lee, Cheng-Yen Wang. 1-4 [doi]
• Low-noise analog synthesis platform for bio-signal acquisition systemYing-Chi Lien, Ching-Mao Lee, Chih-Wei Li, Ban-Han Tsai, Chien-Nan Jimmy Liu. 1-4 [doi]
• A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizerTien-Feng Hsu, Chun-Po Huang, I-Jen Chao, Soon-Jyh Chang. 1-4 [doi]
• An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correctionChe-Min Huang, Tsung-Te Liu, Tzi-Dar Chiueh. 1-4 [doi]
• A configurable wavelet processor for biomedical applicationsWei-Lung Yang, Hsi-Pin Ma. 1-4 [doi]
• Case study of process and design performance debugging with Digital Speed SensorChao-Wen Tzeng, Yin-Yen Chen, Jih-Nung Lee, Shu-Yi Kao. 1-4 [doi]
• A 84.7-DR wide BW incremental ADC using CT structureTing-Yang Wang, Tai-Cheng Lee. 1-4 [doi]
• Diagnosing timing related cell internal defects for FinFET technologyHuaxing Tang, Ting-Pu Tai, Wu-Tung Cheng, Brady Benware, Friedrich Hapke. 1-4 [doi]
• An effective matrix compression method for GPU-accelerated thermal analysisLih-Yih Chiou, Liang-Ying Lu, Chieh-Yu Lin. 1-4 [doi]
• BRAM efficient multi-ported memory on FPGAJiun-Liang Lin, Bo-Cheng Charles Lai. 1-4 [doi]
• Engineered substrates: The foundation to meet current and future RF requirementsJean-Marc Le Meil, Bernard Aspar, Eric Desbonnets, Jean-Pierre Raskin. 1-4 [doi]
• The sum of the parts: Overcoming leading edge design challenges by working in partnershipTim Whitfield. 1 [doi]
• Trinocular adaptive window size disparity estimation algorithm and its real-time hardwareAbdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Ipek Baz, Alexandre Schmid, Yusuf Leblebici. 1-4 [doi]
• Dynamic voltage assignment for thermal-constrained task scheduler on 3D multi-core processorsChien-Hui Liao, Yu-Ze Lin, Charles H.-P. Wen. 1-4 [doi]
• The applications of power integrated circuits with energy savingTsorng-Juu Liang. 1 [doi]
• Energy efficient design and energy harvesting for energy autonomous systemsMakoto Takamiya. 1-3 [doi]
• A test-application-count based learning technique for test time reductionGuo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng. 1-4 [doi]
• Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraintsAnirban Sengupta, Saumya Bhadauria. 1-4 [doi]
• Tunable and reconfigurable solutions using RFSOI-on-HR-Si technologiesJúlio Costa. 1 [doi]
• Full-custom all-digital phase locked loop for clock generationMu-lee Huang, Chung-Chih Hung. 1-4 [doi]
• A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operationYung-Hui Yu, Po-Hao Wang, Shang-Jen Tsai, Tien-Fu Chen. 1-4 [doi]
• Biomedical devices and instruments for point-of-care diagnosisYu-Hwa Lo. 1 [doi]
• A time delay integration CMOS image sensor with online deblurring algorithmHang Yu, Xinyuan Qian, Menghan Guo, Shoushun Chen, Kay-Soon Low. 1-4 [doi]
• Energy-harvesting microsystemsGabriel A. Rincón-Mora. 1 [doi]
• A hybrid built-in self-test scheme for DRAMsChi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou. 1-4 [doi]
• DC-to-5-GHz variable gain amplifier for high speed DSOYu-Lee Yen, Chien-Nan Kuo, Ching-Feng Lee, Kevin Chen. 1-4 [doi]
• Accurate 3-D capacitance extractions for advanced nanometer CMOS nodesKeh-Jeng Chang, Shih-Hao Lee, Kuo-Fu Lee, Ping-Hung Yuh, Ho-Che Yu, Wen-Cheng Huang, Victor C. Y. Chang. 1-4 [doi]