Jovanka Ciric, Gin Yee, Carl Sechen. Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. In 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France. pages 277-282, IEEE Computer Society, 2000. [doi]
Abstract is missing.