Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Jovanka Ciric, Gin Yee, Carl Sechen. Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. In 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France. pages 277-282, IEEE Computer Society, 2000. [doi]

This author has not been identified. Look up 'Jovanka Ciric' in GoogleThis author has not been identified. Look up 'Gin Yee' in GoogleThis author has not been identified. Look up 'Carl Sechen' in Google

runs on WebDSL