Abstract is missing.
- Architectures for High Dynamic Range, High Speed Image Sensor Readout CircuitsSam Kavusi, Kunal Ghosh, Abbas El Gamal. 1-23 [doi]
- Oversampled Time Estimation Techniques for Precision Photonic DetectorsRobert K. Henderson, Bruce Rae, David R. Renshaw, Edoardo Charbon. 25-35 [doi]
- Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon DevicesCarlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, A. Nascetti, Davide Caputo, A. De Cesare. 37-53 [doi]
- Electronic Detection of DNA Adsorption and HybridizationUlrich Bockelmann. 55-67 [doi]
- Probabilistic amp; Statistical Design - the Wave of the FutureShekhar Borkar. 69-79 [doi]
- A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCsShan Jiang, Manh Anh Do, Kiat Seng Yeo. 81-99 [doi]
- Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC DesignLakshmi N. Chakrapani, Jason George, Bo Marr, Bilge E. S. Akgul, Krishna V. Palem. 101-118 [doi]
- Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System DesignAntonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene. 119-141 [doi]
- Soft Error Resilient System Design through Error CorrectionSubhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim. 143-156 [doi]
- Library Compatible Variational Delay ComputationLuís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira. 157-176 [doi]
- A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip ArchitecturesGiovanni Beltrame, Donatella Sciuto, Cristina Silvano. 177-196 [doi]
- Frequency and Speed Setting for Energy Conservation in Autonomous Mobile RobotsJeff Brateman, Changjiu Xian, Yung-Hsiang Lu. 197-216 [doi]
- Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog ComputationZeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz. 217-240 [doi]
- Logic Synthesis of EXOR Projected Sum of ProductsAnna Bernasconi, Valentina Ciriani, Roberto Cordone. 241-257 [doi]
- A Method for I/O Pins Partitioning Targeting 3D VLSI CircuitsRenato Fernandes Hentschke, Sandro Sawicki, Marcelo de Oliveira Johann, Ricardo Reis. 259-279 [doi]
- CAT Platform for Analogue and Mixed-Signal Test Evaluation and OptimizationAhcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu. 281-300 [doi]
- Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test GenerationTsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara. 301-316 [doi]
- Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case StudiesArno Moonen, Chris Bartels, Marco Bekooij, René van den Berg, Harpreet Bhullar, Kees Goossens, Patrick Groeneveld, Jos Huisken, Jef L. van Meerbergen. 317-336 [doi]
- Designing Routing and Message-Dependent Deadlock Free Networks on ChipsSrinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo. 337-355 [doi]
- Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor ModelIttetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai. 357-376 [doi]
- Human++: Emerging Technology for Body Area NetworksJulien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov. 377-397 [doi]