Abstract is missing.
- Beyond gaming: programming the PLAYSTATION®3 cell architecture for cost-effective parallel processingRodric M. Rabbah. 1 [doi]
- Compiling code accelerators for FPGAsWalid A. Najjar. 2 [doi]
- Simultaneous synthesis of buses, data mapping and memory allocation for MPSoCBrett H. Meyer, Donald E. Thomas. 3-8 [doi]
- A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCsMark Thompson, Hristo Nikolov, Todor Stefanov, Andy D. Pimentel, Cagkan Erbas, Simon Polstra, Ed F. Deprettere. 9-14 [doi]
- Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedulesChengmo Yang, Alex Orailoglu. 15-20 [doi]
- Synchronization after design refinements with sensitive delay elementsTarvo Raudvere, Ingo Sander, Axel Jantsch. 21-26 [doi]
- Embedded software development on top of transaction-level modelsWolfgang Klingauf, Robert Günzel, Christian Schröder. 27-32 [doi]
- Pointer re-coding for creating definitive MPSoC modelsPramod Chandraiah, Rainer Dömer. 33-38 [doi]
- Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systemsHiroaki Inoue, Akihisa Ikeno, Tsuyoshi Abe, Junji Sakai, Masato Edahiro. 39-44 [doi]
- Secure FPGA circuits using controlled placement and routingPengyuan Yu, Patrick Schaumont. 45-50 [doi]
- A smart random code injection to mask power analysis based side channel attacksJude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran. 51-56 [doi]
- Ensuring secure program execution in multiprocessor embedded systems: a case studyKrutartha Patel, Sridevan Parameswaran, Seng Lin Shee. 57-62 [doi]
- Combined approach to system level performance analysis of embedded systemsSimon Künzli, Arne Hamann, Rolf Ernst, Lothar Thiele. 63-68 [doi]
- Event-based re-training of statistical contention models for heterogeneous multiprocessorsAlex Bobrek, JoAnn M. Paul, Donald E. Thomas. 69-74 [doi]
- HySim: a fast simulation framework for embedded software developmentStefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 75-80 [doi]
- A computational reflection mechanism to support platform debugging in SystemCBruno Albertini, Sandro Rigo, Guido Araujo, Cristiano C. de Araujo, Edna Barros, Willians Azevedo. 81-86 [doi]
- Energy efficient co-scheduling in dynamically reconfigurable systemsPao-Ann Hsiung, Pin-Hsien Lu, Chih-Wen Liu. 87-92 [doi]
- Thread warping: a framework for dynamic synthesis of thread acceleratorsGreg Stitt, Frank Vahid. 93-98 [doi]
- HW/SW co-design for Esterel processingSascha Gädtke, Claus Traulsen, Reinhard von Hanxleden. 99-104 [doi]
- Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systemsSeunghoon Kim, Robert P. Dick, Russ Joseph. 105-110 [doi]
- Temperature-aware processor frequency assignment for MPSoCs using convex optimizationSrinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen P. Boyd, Giovanni De Micheli. 111-116 [doi]
- Three-dimensional multiprocessor system-on-chip thermal optimizationChong Sun, Li Shang, Robert P. Dick. 117-122 [doi]
- Complexity challenges towards 4th generation communication solutionsHermann Eul. 123 [doi]
- Fresh air: the emerging landscape of design for networked embedded systemsRadu Marculescu, Borivoje Nikolic, Alberto L. Sangiovanni-Vincentelli. 124 [doi]
- Locality optimization in wireless applicationsJaved Absar, Min Li, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Arnout Vandecappelle, Francky Catthoor. 125-130 [doi]
- A code-generator generator for multi-output instructionsHanno Scharwächter, Jonghee M. Yoon, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr. 131-136 [doi]
- Influence of procedure cloning on WCET predictionPaul Lokuciejewski, Heiko Falk, Martin Schwarzer, Peter Marwedel, Henrik Theiling. 137-142 [doi]
- Compile-time decided instruction cache locking using worst-case execution pathsHeiko Falk, Sascha Plazar, Henrik Theiling. 143-148 [doi]
- Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chipAndreas Hansson, Martijn Coenen, Kees Goossens. 149-154 [doi]
- Performance and resource optimization of NoC router architecture for master and slave IP coresGlenn Leary, Krishna Mehta, Karam S. Chatha. 155-160 [doi]
- Incremental run-time application mapping for homogeneous NoCs with multiple voltage levelsChen-Ling Chou, Radu Marculescu. 161-166 [doi]
- A data protection unit for NoC-based architecturesLeandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano. 167-172 [doi]
- Complex task activation schemes in system level performance analysisWolfgang Haid, Lothar Thiele. 173-178 [doi]
- Improved response time analysis of tasks scheduled under preemptive Round-RobinRazvan Racu, Li Li, Rafik Henia, Arne Hamann, Rolf Ernst. 179-184 [doi]
- Probabilistic performance risk analysis at system-levelAlexander Viehl, Markus Schwarz, Oliver Bringmann, Wolfgang Rosenstiel. 185-190 [doi]
- ESL design and HW/SW co-verification of high-end software defined radio platformsA. C. H. Ng, J. W. Weijers, Miguel Glassee, Thomas Schuster, Bruno Bougard, Liesbet Van der Perre. 191-196 [doi]
- Smart driver for power reduction in next generation bistable electrophoretic display technologyMichael A. Baker, Aviral Shrivastava, Karam S. Chatha. 197-202 [doi]
- On the impact of manufacturing process variations on the lifetime of sensor networksSiddharth Garg, Diana Marculescu. 203-208 [doi]
- Performance modeling for early analysis of multi-core systemsReinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han. 209-214 [doi]
- Bridging gap between simulation and spreadsheet studyAntoine Perrin, Frank Ghenassia. 215-216 [doi]
- Performance analysis and design space exploration for high-end biomedical applications: challenges and solutionsIyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luca Benini. 217-226 [doi]
- A low power VLIW processor generation method by means of extracting non-redundant activation conditionsHirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 227-232 [doi]
- Scheduling and voltage scaling for energy/reliability trade-offs in fault-tolerant time-triggered embedded systemsPaul Pop, Kåre Harbo Poulsen, Viacheslav Izosimov, Petru Eles. 233-238 [doi]
- Reliable multiprocessor system-on-chip synthesisChangyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, Li Shang. 239-244 [doi]
- Aggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processorsChenjie Yu, Peter Petrov. 245-250 [doi]
- Predator: a predictable SDRAM memory controllerBenny Akesson, Kees Goossens, Markus Ringhofer. 251-256 [doi]
- Performance improvement of block based NAND flash translation layerSiddharth Choudhuri, Tony Givargis. 257-262 [doi]
- Automotive networks: are new busses and gateways the answer or just another challenge?Rolf Ernst, Gernot Spiegelberg, Thomas Weber, Hermann Kopetz, Alberto L. Sangiovanni-Vincentelli, Marek Jersak. 263 [doi]