Abstract is missing.
- An Image Recognition System for Multiple Video Inputs over a Multi-FPGA SystemTakuya Otsuka, Takashi Aoki, Eiichi Hosoya, Akira Onozawa. 1-7 [doi]
- Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic ProgrammingJunko Tazawa, Yuichi Okuyama, Yuichi Yaguchi, Toshiaki Miyazaki, Ryuichi Oka, Kenichi Kuroda. 8-15 [doi]
- Hardware Accelerator for BLASTShizuka Ishikawa, Asuka Tanaka, Toshiaki Miyazaki. 16-22 [doi]
- DLWAP-buffer: A Novel HW/SW Architecture to Alleviate the Cache Coherence on Streaming-like Data in CMPXiaoping Huang, Xiaoya Fan, Shengbing Zhang, Yuhui Chen. 23-28 [doi]
- On-chip Communication Buffer Architecture Optimization Considering Bus WidthSalita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 29-36 [doi]
- Throttling Control for Bufferless Routing in On-chip NetworksYicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga. 37-44 [doi]
- Transputer-like Multicore Digital Signal Processing on the Array of ARM Cortex-M0 MicroprocessorsKunio Takaya. 45-50 [doi]
- FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and OptimizationsWeihua Sheng, Artur Wiebe, Anastasia Stulova, Rainer Leupers, Bart Kienhuis, Johan Walters, Gerd Ascheid. 51-58 [doi]
- Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline RouterTakeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano. 59-66 [doi]
- Segmented Bus Based Path Setup Scheme for a Distributed Memory ArchitectureMuhammad Adeel Tajammul, Muhammad Ali Shami, Ahmed Hemani. 67-74 [doi]
- GRAPE-MPs: Implementation of an SIMD for Quadruple/Hexuple/Octuple-Precision Arithmetic Operation on a Structured ASIC and an FPGANaohito Nakasato, Hiroshi Daisaka, Toshiyuki Fukushige, Atsushi Kawai, Junichiro Makino, Tadashi Ishikawa, Fukuko Yuasa. 75-83 [doi]
- Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGAYasin Oge, Takefumi Miyoshi, Hideyuki Kawashima, Tsutomu Yoshinaga. 84-91 [doi]
- Removing Context Memory from a Multi-context Dynamically Reconfigurable ProcessorHideharu Amano, Masayuki Kimura, Nobuaki Ozaki. 92-99 [doi]
- An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-ChipHiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura. 100-106 [doi]
- Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network CongestionSho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 107-112 [doi]
- Scheduling for Multi-core Processor under Process and Temperature VariationZheng Zhou 0002, Junjun Gu, Gang Qu. 113-120 [doi]
- Optimal Assignment for Tree-Structure Task Graph on Heterogeneous Multicore Systems Considering Time ConstraintLi Wang, Jing Liu, Jingtong Hu, Qingfeng Zhuge, Edwin Hsing-Mean Sha. 121-127 [doi]
- Multi-decision Making Based PSO Optimization in Airborne Mobile Sensor Network DeploymentXuanya Li, Linlin Ci, Minghua Yang, Hongyu Wei, Chengping Tian, Bin Cheng. 128-134 [doi]
- A Novel Data Transfer Scheme of Smart Grid and DTNHong Yao, Zheng Zhao, Huawei Huang, Lei Cong. 135-138 [doi]
- Design of a Safety Confirmation System Integrating Wireless Sensor Network and Smart Phones for DisasterJunbo Wang, Zixue Cheng, Isao Nishiyama, Yinghui Zhou. 139-143 [doi]
- Accurate Coverage of Complex Targets in Three-Dimensional Mobile Sensor NetworksXiang Li, Xuanya Li. 144-150 [doi]
- Early Stage Chick Embryonic Heart Outflow Tract Flow Measurement Using High Speed 4D Optical Coherence TomographyZhenhe Ma, Tao Xu, LinLin Du, Zhongdi Chu, Jiangtao Lv, Fengwen Wang. 151-154 [doi]
- Load-Prediction Parallelization for Computer Simulation of Electrocardiogram Based on GPUWenfeng Shen, Liang Wang, Jie Li, Weimin Xu, Daming Wei, Xin Zhu. 155-158 [doi]
- Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous ChannelsNicola Caselli, Alessandro Strano, Daniele Ludovici, Davide Bertozzi. 159-166 [doi]
- LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) ArchitectureAkram Ben Ahmed, Abderazek Ben Abdallah. 167-174 [doi]
- Path-Diversity-Aware Adaptive Routing in Network-on-Chip SystemsYu-Hsin Kuo, Po-An Tsai, Hao-Ping Ho, En-Jui Chang, Hsien-Kai Hsin, An-Yeu Andy Wu. 175-182 [doi]
- An Auto-Tuning Technique of the Weighted Jacobi-Type Iteration Used for Preconditioners of Krylov Subspace MethodsAkira Imakura, Tetsuya Sakurai, Kohsuke Sumiyoshi, Hideo Matsufuru. 183-190 [doi]
- SSG-AT: An Auto-tuning Method of Sparse Matrix-vector Multiplicataion for Semi-structured Grids - An Adaptation to OpenFOAMSatoshi Ito, Satoshi Ohshima, Takahiro Katagiri. 191-197 [doi]
- Implementing a Code Generator for Fast Matrix Multiplication in OpenCL on the GPUKazuya Matsumoto, Naohito Nakasato, Stanislav G. Sedukhin. 198-204 [doi]
- Tuning Block Size for QR Factorization on CPU-GPU Hybrid SystemsYaohung M. Tsai, Weichung Wang, Ray-Bing Chen. 205-211 [doi]