Abstract is missing.
- The Transmeta Crusoe: VLIW Embedded in CISCJames C. Dehnert. 1 [doi]
- Limited Address Range Architecture for Reducing Code Size in Embedded ProcessorsQin Zhao, Bart Mesman, Henk Corporaal. 2-16 [doi]
- Predicated Instructions for Code CompactionWarren Cheung, William S. Evans, Jeremy Moses. 17-32 [doi]
- Code Generation for a Dual Instruction Set Processor Based on Selective Code TransformationSheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson. 33-48 [doi]
- Code Instruction Selection Based on SSA-GraphsErik Eckstein, Oliver König, Bernhard Scholz. 49-65 [doi]
- A Code Selection Method for SIMD Processors with PACK InstructionsHiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai. 66-80 [doi]
- Reconstructing Control Flow from Predicated Assembly CodeBjörn Decker 0002, Daniel Kästner. 81-100 [doi]
- Control Flow Analysis for Recursion RemovalStefaan Himpe, Francky Catthoor, Geert Deconinck. 101-116 [doi]
- An Unfolding-Based Loop Optimization TechniqueLitong Song, Krishna M. Kavi, Ron Cytron. 117-132 [doi]
- Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop BufferGang-Ryung Uh. 133-150 [doi]
- Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code GenerationYunheung Paek, Minwook Ahn, Soonho Lee. 151-166 [doi]
- Extraction of Efficient Instruction Schedulers from Cycle-True Processor ModelsOliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie. 167-181 [doi]
- A Framework for the Design and Validation of Efficient Fail-Safe Fault-Tolerant ProgramsArshad Jhumka, Neeraj Suri, Martin Hiller. 182-197 [doi]
- A Case Study on a Component-Based System and Its ConfigurationHiroo Ishikawa, Tatsuo Nakajima. 198-210 [doi]
- Composable Code Generation for Model-Based DevelopmentKirk Schloegel, David Oglesby, Eric Engstrom, Devesh Bhatt. 211-225 [doi]
- Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network ProcessorIoannis Charitakis, Dionisios N. Pnevmatikatos, Evangelos P. Markatos, Kostas G. Anagnostakis. 226-239 [doi]
- Retargetable Graph-Coloring Register Allocation for Irregular ArchitecturesJohan Runeson, Sven-Olof Nyström. 240-254 [doi]
- Fine-Grain Register Allocation Based on a Global Spill Costs AnalysisDae-Hwan Kim, Hyuk-Jae Lee. 255-269 [doi]
- Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset AssignmentV. V. N. S. Sarvani, R. Govindarajan. 270-284 [doi]
- Improving Offset Assignment through Simultaneous Variable CoalescingDesiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers. 285-297 [doi]
- Transformation of Meta-Information by Abstract Co-interpretationRaimund Kirner, Peter P. Puschner. 298-312 [doi]
- Performance Analysis for Identification of (Sub-)Task-Level Parallelism in JavaRichard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor. 313-328 [doi]
- Towards Superinstructions for Java InterpretersKevin Casey, David Gregg, M. Anton Ertl, Andrew Nisbet. 329-343 [doi]
- Partitioning for DSP Software SynthesisMing-Yung Ko, Shuvra S. Bhattacharyya. 344-358 [doi]
- Efficient Variable Allocation to Dual Memory Banks of DSPsViera Sipková. 359-372 [doi]
- Cache Behavior Modeling of Codes with Data-Dependent ConditionalsDiego Andrade, Basilio B. Fraguela, Ramon Doallo. 373-387 [doi]
- FICO: A Fast Instruction Cache OptimizerMarco Garatti. 388-402 [doi]