An Asynchronous Synthesis Toolset Using Verilog - researchr publication

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Frank P. Burns, Delong Shang, Albert Koelmans, Alexandre Yakovlev. An Asynchronous Synthesis Toolset Using Verilog. In 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France. pages 724-725, IEEE Computer Society, 2004. [doi]

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