Chen-Huan Chiang, Sandeep K. Gupta. BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. In 15th IEEE VLSI Test Symposium (VTS 97), April 27-May 1, 1997, Monterey, California, USA. pages 376-383, IEEE Computer Society, 1997. [doi]
Abstract is missing.