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Chen-Huan Chiang, Sandeep K. Gupta. BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. In 15th IEEE VLSI Test Symposium (VTS 97), April 27-May 1, 1997, Monterey, California, USA. pages 376-383, IEEE Computer Society, 1997. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board LevelChen-Huan Chiang, Sandeep K. Gupta. ats 1998: 244-252 [doi] BIST TPG for Combinational Cluster Interconnect Testing at Board LevelChen-Huan Chiang, Sandeep K. Gupta. et, 16(5):427-442, 2000. [doi] BIST TPG for SRAM cluster interconnect testing at board levelChen-Huan Chiang, Sandeep K. Gupta. ats 2000: 58-65 [doi] BIST TPG for faults in system backplanesChen-Huan Chiang, Sandeep K. Gupta. iccad 1997: 406-413 [doi]
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