Chen-Huan Chiang, Sandeep K. Gupta. BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. In 15th IEEE VLSI Test Symposium (VTS 97), April 27-May 1, 1997, Monterey, California, USA. pages 376-383, IEEE Computer Society, 1997. [doi]
@inproceedings{ChiangG97:0,
title = {BIST TPGs for Faults in Board Level Interconnect via Boundary Scan},
author = {Chen-Huan Chiang and Sandeep K. Gupta},
year = {1997},
url = {http://csdl.computer.org/comp/proceedings/vts/1997/7810/00/78100376abs.htm},
researchr = {https://researchr.org/publication/ChiangG97%3A0},
cites = {0},
citedby = {0},
pages = {376-383},
booktitle = {15th IEEE VLSI Test Symposium (VTS 97), April 27-May 1, 1997, Monterey, California, USA},
publisher = {IEEE Computer Society},
}