An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou. A formal method to improve SystemVerilog functional coverage. In 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012, Huntington Beach, CA, USA, November 9-10, 2012. pages 56-63, IEEE Computer Society, 2012. [doi]
Abstract is missing.