Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection

Nur A. Touba, Edward J. McCluskey. Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. In Jochen A. G. Jess, Richard L. Rudell, editors, Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994, San Jose, California, USA, November 6-10, 1994. pages 651-654, IEEE Computer Society, 1994. [doi]

Abstract

Abstract is missing.