Abstract is missing.
- Next-generation consumer audio application specific embedded processorJi Kong, Peilin Liu, Xianmin Chen, Jin Wang, Xingguang Pan, Jun Wang, He Xiao, Zhenqi Wei, Rendong Ying. 1-7 [doi]
- CMA: Chip multi-acceleratorDominik Auras, Sylvain Girbal, Hugues Berry, Olivier Temam, Sami Yehia. 8-15 [doi]
- Processor accelerator for AESRuby B. Lee, Yu-Yuan Chen. 16-21 [doi]
- A hardware pipeline for accelerating ray traversal algorithms on streaming processorsMichael Steffen, Joseph Zambreno. 22-29 [doi]
- Ultra low energy Domain Specific Instruction-set Processor for on-line surveillanceDavid Novo, Angeliki Kritikakou, Praveen Raghavan, Liesbet Van der Perre, Jos Huisken, Francky Catthoor. 30-35 [doi]
- Customized architectures for faster route finding in GPS-based navigation systemsJason Loew, Dmitry Ponomarev, Patrick H. Madden. 36-43 [doi]
- A processing engine for GPS correlationAhmed O. El-Rayis, Tughrul Arslan, Ahmet T. Erdogan. 44-49 [doi]
- A Coarse Grain Reconfigurable Architecture for sequence alignment problems in bio-informaticsPei Liu, Ahmed Hemani. 50-57 [doi]
- An RTOS in hardware for energy efficient software-based TCP/IP processingNaotaka Maruyama, Tohru Ishihara, Hiroto Yasuura. 58-63 [doi]
- FPGA and GPU implementation of large scale SpMVYi Shan, Tianji Wu, Yu Wang 0002, Bo Wang, Zilong Wang, Ningyi Xu, Huazhong Yang. 64-70 [doi]
- Accelerating DNA analysis applications on GPU clustersAntonino Tumeo, Oreste Villa. 71-76 [doi]
- Efficient template matching with variable size templates in CUDANicholas Moore, Miriam Leeser, Laurie A. Smith King. 77-80 [doi]
- I-cache configurability for temperature reduction through replicated cache partitioningMathew Paul, Peter Petrov. 81-86 [doi]
- A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devicesThomas Marconi, Jae Young Hur, Koen Bertels, Georgi Gaydadjiev. 87-92 [doi]
- A dynamically reconfigurable asynchronous processorKhodor Ahmad Fawaz, Tughrul Arslan, Sami Khawam, Mark Muir, Ioannis Nousias, Iain Lindsay, Ahmet T. Erdogan. 93-96 [doi]
- Design of a custom VEE core in a chip multiprocessorDan Upton, Kim M. Hazelwood. 97-100 [doi]
- Minimizing write activities to non-volatile memory via scheduling and recomputationJingtong Hu, Chun Jason Xue, Wei-Che Tseng, Qingfeng Zhuge, Edwin Hsing-Mean Sha. 101-106 [doi]
- Early performance-cost estimation of application-specific data path pipeliningJelena Trajkovic, Daniel D. Gajski. 107-110 [doi]
- Efficient design and generation of a multi-facet arbiterJer Min Jou, Yun-Lung Lee, Sih-Sian Wu. 111-114 [doi]
- Reconfigurable custom functional unit generation and exploitation in multiple-issue processorsHui-Shan Wang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung. 115-118 [doi]