Jae Young Hur - researchr alias

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Viewing Publication 1 - 20 from 20

2023

Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB CoalescingTran Dai Duong, Jae Young Hur. access, 11:91850-91860, 2023. [doi]

2021

Clean-prefetcher: look-ahead prefetching without cache pollutionMinshin Cho, Jae Young Hur, Wooyoung Jang. ieiceee, 18(6):20210027, 2021. [doi]

2020

Virtual Address Remapping with Configurable Tiles in Image Processing ApplicationsJae Young Hur. ieicet, 103-D(2):309-320, 2020. [doi]

Page Table Compaction for TLB CoalescingJae Young Hur, Joonho Kong. access, 8:104814-104829, 2020. [doi]

Near-Threshold L1 Data Cache for Yield Management Under Process VariationsJoonho Kong, Jae Young Hur. access, 8:18558-18570, 2020. [doi]

TLC STT-MRAM aware LLC for multicore processorTaejin Park, Jae Young Hur, Wooyoung Jang. ieiceee, 17(24):20200359, 2020. [doi]

2019

Contiguity Representation in Page Table for Memory Management UnitsJae Young Hur. tvlsi, 27(1):147-158, 2019. [doi]

Block Level TLB Coalescing for Buddy Memory AllocatorJae Young Hur. ieicet, 102-D(10):2043-2046, 2019. [doi]

Adaptive Linear Address Map for Bank Interleaving in DRAMsJae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang. access, 7:129604-129616, 2019. [doi]

2017

Representing Contiguity in Page Table for Memory Management UnitsJae Young Hur. mcsoc 2017: 21-28 [doi]

2012

Customisation of on-chip network interconnects and experiments in field-programmable gate arraysJae Young Hur, Todor Stefanov, Stephan Wong, Kees Goossens. iet-cdt, 6(1):59-68, 2012. [doi]

Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arraysJae Young Hur, Kees Goossens, Lotfi Mhamdi, Muhammad Aqeel Wahlah. iet-cdt, 6(6):396-405, 2012. [doi]

2011

Customizing and hardwiring on-chip interconnects in FPGAsJae Young Hur. PhD thesis, Delft University of Technology, Netherlands, 2011. [doi]

2010

Design Trade-offs in Customized On-chip Crossbar SchedulersJae Young Hur, Stephan Wong, Todor Stefanov. vlsisp, 58(1):69-85, 2010. [doi]

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devicesThomas Marconi, Jae Young Hur, Koen Bertels, Georgi Gaydadjiev. sasp 2010: 87-92 [doi]

2008

Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration InterconnectsKees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah. nocs 2008: 45-54 [doi]

Yeast on a Chip - Single-cell Analyses of MAPK Signaling Pathways in Saccharomyces Cerevisiae using Cell ChipsMin Cheol Park, Moon Kyu Kwak, Hye Sung Cho, Kahp Y. Suh, Jae Young Hur, Sang-Hyun Park. biostec 2008: 268-271

2007

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