Abstract is missing.
- Circuit Design in Nano-Scale CMOS TechnologiesKevin Zhang. 1 [doi]
- Physical Design Automation for 3D Chip Stacks: Challenges and SolutionsJohann Knechtel, Jens Lienig. 3-10 [doi]
- ePlace-3D: Electrostatics based Placement for 3D-ICsJingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng. 11-18 [doi]
- A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing DataHantao Huang, Hao Yu, Cheng Zhuo, Fengbo Ren. 19-25 [doi]
- PLATON: A Force-Directed Placement Algorithm for 3D Optical Networks-on-ChipAnja von Beuningen, Ulf Schlichtmann. 27-34 [doi]
- Optimizing for Power, Speed, Cost and Emissions in Automotive DrivetrainsPatrick R. Groeneveld. 35 [doi]
- Cell-Based Design Methods for Directed Self-AssemblyKarl Berggren, Caroline A. Ross, Hyung Wan Do, Jae-Byum Chang, Hong Kyoon Choi. 37 [doi]
- Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid LithographyJiaojiao Ou, Bei Yu, David Z. Pan. 39-46 [doi]
- Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded DesignsZhi-Wen Lin, Yao-Wen Chang. 47-54 [doi]
- Technology Inflection PointsVictor Moroz. 55 [doi]
- Challenges and Opportunities with Place and Route of Modern FPGA DesignsRaymond X. Nijssen. 57 [doi]
- Design and Tool Flow of IBM's TrueNorth: an Ultra-Low Power Programmable Neurosynaptic Chip with 1 Million NeuronsFilipp Akopyan. 59-60 [doi]
- Some Observations on the Physical Design of the Next DecadeAntun Domic. 61 [doi]
- A Designer's Perspective on Timing ClosureGreg Ford. 63 [doi]
- Cell Selection for High-Performance Designs in an Industrial Design FlowTiago J. Reimann, Cliff C. N. Sze, Ricardo Reis. 65-72 [doi]
- Drive Strength Aware Cell Movement Techniques for Timing Driven PlacementGuilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis. 73-80 [doi]
- Construction of Latency-Bounded Clock TreesRickard Ewetz, Chuan Yean Tan, Cheng-Kok Koh. 81-88 [doi]
- Scaling Beyond 7nm: Design-Technology Co-optimization at the RescueJulien Ryckaert. 89 [doi]
- Proximity Optimization for Adaptive Circuit DesignAng Lu, Hao He, Jiang Hu. 91-97 [doi]
- Load-Aware Redundant Via Insertion for Electromigration AvoidanceSteve Bigalke, Jens Lienig. 99-106 [doi]
- Early Days of Automatic Floorplan DesignMartin D. F. Wong. 107 [doi]
- The Annealing Algorithm revistedLukas P. P. P. van Ginneken. 109-111 [doi]
- Trailblazing Physical Design Flows: Ralph Otten's Impact on Design AutomationPatrick R. Groeneveld. 113 [doi]
- Complexity and Diversity in IC Layout DesignRalph Otten. 115 [doi]
- An Interactive Physical Synthesis Methodology for High-Frequency FPGA DesignsSabya Das, Rajat Aggarwal, Zhiyong Wang. 117-122 [doi]
- Power Optimization of FPGA Interconnect Via Circuit and CAD TechniquesSafeen Huda, Jason Helge Anderson. 123-130 [doi]
- Scaling Up Physical Design: Challenges and OpportunitiesGuojie Luo, Wentai Zhang, Jiaxi Zhang, Jason Cong. 131-137 [doi]
- Routability-Driven FPGA Placement ContestStephen Yang, Aman Gayasen, Chandra Mulpuri, Sainath Reddy, Rajat Aggarwal. 139-143 [doi]
- Generating Routing-Driven Power Distribution Networks with Machine-Learning TechniqueWen-Hsiang Chang, Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu, Mango Chia-Tso Chao, Cheng-Hong Tsai, Yen-Chih Chiu. 145-152 [doi]
- Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region CoverageWei Wu, Srinivas Bodapati, Lei He. 153-160 [doi]
- A Machine Learning Based Framework for Sub-Resolution Assist Feature GenerationXiaoqing Xu, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan. 161-168 [doi]