Table of Contents

• Challenges and Opportunities for FPGA Programmable System PlatformsIvo Bolsens. 3 [doi]
• Technology Scaling Trends and Accelerated Testing for Soft Errors in Commercial Silicon DevicesRobert Baumann. 4 [doi]
• Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-ICYi Zhao, Sujit Dey. 7-11 [doi]
• A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICsY. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis. 12-16 [doi]
• On-Line Error Detecting Constant Delay AdderWhitney J. Townsend, Jacob A. Abraham, Parag K. Lala. 17 [doi]
• A Modulo p Checked Self-Checking Carry Select AdderVitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld. 25-29 [doi]
• Foundation of Combined Datapath and Controller Self-checking DesignPetros Oikonomakos, Mark Zwolinski. 30-34 [doi]
• Synthesis of Low-Cost Parity-Based Partially Self-Checking CircuitsKartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba. 35 [doi]
• A Design Method for Embedded Self-Testing t-UED and BUED Code CheckersSteffen Tarnick. 43-48 [doi]
• Designing FPGA based Self-Testing Checkers for m-out-of-n CodesA. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. Nikitin. 49-53 [doi]
• An Analog Checker With Input-Relative Tolerance for Duplicate SignalsHaralampos-G. D. Stratigopoulos, Yiorgos Makris. 54 [doi]
• Power Consumption of Fault Tolerant Codes: the Active ElementsDaniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra. 61-67 [doi]
• On the Probability of Detecting Data Errors Generated by Permanent Faults Using Time RedundancyJoakim Aidemark, Peter Folkesson, Johan Karlsson. 68-74 [doi]
• The positive effect on IC yield of embedded Fault Tolerance for SEUsAndré K. Nieuwland, Richard P. Kleihorst. 75 [doi]
• On-Line Testable Decimation Filter Design for AMS SystemsMohammad A. Naal, Emmanuel Simeu, Salvador Mir. 83-88 [doi]
• An Efficient BIST scheme for High-Speed AddersD. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou. 89-93 [doi]
• Memory Built-In Self-Repair for NanotechnologiesMichael Nicolaidis, Nadir Achouri, Lorena Anghel. 94 [doi]
• Accurate and Efficient Analysis of Single Event Transients in VLSI CircuitsMatteo Sonza Reorda, Massimo Violante. 101-105 [doi]
• An Improved Markov Source Design for Scan BISTChaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz. 106-110 [doi]
• A Model for Transient Fault Propagation in Combinatorial LogicMartin Omaña, Giacinto Papasso, Daniele Rossi, Cecilia Metra. 111 [doi]
• Analyzing SEU Effects in SRAM-based FPGAsMassimo Violante, M. Ceschia, Matteo Sonza Reorda, Alessandro Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori. 119-123 [doi]
• Defect Analysis for Delay-Fault BIST in FPGAsPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. 124-128 [doi]
• A Fault Injection Tool for SRAM-based FPGAsMonica Alderighi, Sergio D Angelo, Marcello Mancini, Giacomo R. Sechi. 129 [doi]
• Low-Cost On-Line Fault Detection Using Control Flow AssertionsRajesh Venkatasubramanian, John P. Hayes, Brian T. Murray. 137-143 [doi]
• A Watchdog Processor to Detect Data and Control Flow ErrorsAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 144-148 [doi]
• Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor CoresGeorge Xenoulis, Dimitris Gizopoulos, Nektarios Kranitis, Antonis M. Paschalis. 149 [doi]
• On Compaction-Based Concurrent Error DetectionSobeeh Almukhaizim, Petros Drineas, Yiorgos Makris. 157 [doi]
• Increasing Implementability of beta-driven Threshold CheckersVictor Varshavsky, Ilya Levin, Vladimir Ostrovsky. 158 [doi]
• An RT-level Concurrent Error Detection Technique for Data Dominated SystemsO. Goloubeva, Matteo Sonza Reorda, Massimo Violante. 159 [doi]
• FAUST: FAUlt-injection Script-based ToolAlfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, I. Solcia, Luca Tagliaferri. 160 [doi]
• Fault Injection in Digital Logic Circuits at the VHDL LevelS. R. Seward, Parag K. Lala. 161 [doi]
• Radiation test methodology for SRAM-based FPGAs by using THESICMonica Alderighi, Fabio Casini, Sergio D Angelo, F. Faure, Marcello Mancini, Sandro Pastore, Giacomo R. Sechi, Raoul Velazco. 162 [doi]
• Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy?Fabian Vargas, Diogo B. Brum, Dárcio Prestes, Leticia Maria Veiras Bolzani, Eduardo Luis Rhod, Matteo Sonza Reorda. 163 [doi]
• Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe SystemsFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 164-165 [doi]
• Analysis of Bit Transition Count for EDAC Encoded FSMN. Venkateswaran, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu. 166 [doi]
• A Configurable Built in Current Sensor for Mixed Signal Circuit TestingRodrigo Picos, Joan Font, Eugeni Isern, Miquel Roca, Eugenio García. 167 [doi]
• Evaluation of the Quality of Testing Path Delay Faults under Restricted Input AssumptionAndrzej Krasniewski. 168 [doi]
• Control Signal Protection For High Performance ProcessorsMatthias Pflanz, Heinrich Theodor Vierhaus. 173 [doi]
• An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current TestingB. Alorda, Jaume Segura. 178-182 [doi]
• Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a ChipChristian Galke, Marcus Grabow, Heinrich Theodor Vierhaus. 183 [doi]
• On a Redundant Diversified Steering AngleElmar Dilger, Matthias Gulbins, Thomas Ohnesorge, Bernd Straube. 191-196 [doi]
• Automatic toolset for fault tolerant design: results demonstration on a running industrial applicationAlberto Manzone, Claudio Genta. 197-201 [doi]
• Error-Injection-Based Failure Characterization of the IEEE 1394 BusD. J. Beauregard, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Savio N. Chau, Leon Alkalai. 202 [doi]
• A Methodology for Test Replacement Solutions of Obsolete ProcessorsRaoul Velazco, Lorena Anghel, S. Saleh. 209-213 [doi]
• Crosstalk Effect Minimization for Encoded BussesL. Di Silvio, Daniele Rossi, Cecilia Metra. 214-218 [doi]
• InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCsDimitri Kagaris, Spyros Tragoudas. 219-224 [doi]