Interconnection Delay and Clock Cycle Selection in High Level Synthesis - researchr publication

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Hortensia Mecha, Milagros Fernández. Interconnection Delay and Clock Cycle Selection in High Level Synthesis. In 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India. pages 504-505, IEEE Computer Society, 1997. [doi]

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