Optimal Clock Period for Synthesized Data Paths

A. R. Naseer, M. Balakrishnan, Anshul Kumar. Optimal Clock Period for Synthesized Data Paths. In 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India. pages 134-139, IEEE Computer Society, 1997. [doi]

Abstract

Abstract is missing.