Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis

Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa. Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. In 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India. pages 151-156, IEEE Computer Society, 1999. [doi]

Abstract

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