Prashant Saxena, Peichen Pan, C. L. Liu. The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. In 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India. pages 402-407, IEEE Computer Society, 1999. [doi]
Abstract is missing.