Abstract is missing.
- On wirelength estimations for row-based placementAndrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky. 4-11 [doi]
- Performance-driven soft-macro clustering and placement by preserving HDL design hierarchyHsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin. 12-17 [doi]
- Nostradamus: a floorplanner of uncertain designKia Bazargan, Samjung Kim, Majid Sarrafzadeh. 18-23 [doi]
- Timing metrics for physical design of deep submicron technologiesLawrence T. Pileggi. 28-33 [doi]
- Moore s law and physical design of ICsWojciech Maly. 36 [doi]
- Greedy wire-sizing is linear timeChris C. N. Chu, D. F. Wong. 39-44 [doi]
- An efficient technique for device and interconnect optimization in deep submicron designsJason Cong, Lei He. 45-51 [doi]
- Device-level early floorplanning algorithms for RF circuitsMehmet Aktuna, Rob A. Rutenbar, L. Richard Carley. 57-64 [doi]
- A layout approach to monolithic microwave ICAkira Nagao, Takashi Kambe, Isao Shirakawa. 65-72 [doi]
- CHDStd - application support for reusable hierarchical interconnect timing viewsS. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, D. Cottrell, D. Mallis, S. DasGupta, J. Morrell, Amrich Chokhavtia. 75-79 [doi]
- Critical area computation - a new approachEvanthia Papadopoulou, D. T. Lee. 89-94 [doi]
- Filling and slotting: analysis and algorithmsAndrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky. 95-102 [doi]
- Global wires: harmful?Ralph H. J. M. Otten. 104-109 [doi]
- Partitioning using second-order information and stochastic-gain functionsShantanu Dutt, Halim Theny. 112-117 [doi]
- A parallel algorithm for zero skew clock tree routingZhaoyun Xing, Prithviraj Banerjee. 118-123 [doi]
- A pattern matching algorithm for verification and analysis of very large IC layoutsMariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas. 129-134 [doi]
- LIBRA - a library-independent framework for post-layout performance optimizationChung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng. 135-140 [doi]
- Estimation of maximum current envelope for power bus analysis and designSudhakar Bobba, Ibrahim N. Hajj. 141-146 [doi]
- New efficient algorithms for computing effective capacitanceAndrew B. Kahng, Sudhakar Muddu. 147-151 [doi]
- Calculation of ramp response of lossy transmission lines using two-port network functionsPayam Heydari, Massoud Pedram. 152-157 [doi]
- Switch-matrix architecture and routing for FPDsGuang-Ming Wu, Yao-Wen Chang. 158-163 [doi]
- Sequence-pair based placement method for hard/soft/pre-placed modulesHiroshi Murata, Ernest S. Kuh. 167-172 [doi]
- Rectilinear block placement using sequence-pairJin Xu, Pei-Ning Guo, Chung-Kuan Cheng. 173-178 [doi]
- Topology constrained rectilinear block packing for layout reuseMaggie Zhiwei Kang, Wayne Wei-Ming Dai. 179-186 [doi]
- Futures for partitioning in physical design (tutorial)Andrew B. Kahng. 190-193 [doi]
- Chip-level area routingLe-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen. 197-204 [doi]
- Analysis, reduction and avoidance of crosstalk on VLSI chipsTilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl. 211-218 [doi]